> Date: Wed, 25 Jul 2018 00:01:18 +0200 (CEST)
> From: Mark Kettenis <[email protected]>
>
> Diff below switches to the MI equivalent and kills the MD-specific
> API.
>
> ok?
Here is the equivalent i386 diff. Only compile-tested so I'd
appreciate it if somebody can test this for me. Do test
suspend/resume and hibernate.
Index: arch/i386/i386/apm.c
===================================================================
RCS file: /cvs/src/sys/arch/i386/i386/apm.c,v
retrieving revision 1.117
diff -u -p -r1.117 apm.c
--- arch/i386/i386/apm.c 17 Aug 2017 19:44:27 -0000 1.117
+++ arch/i386/i386/apm.c 27 Jul 2018 23:10:46 -0000
@@ -247,7 +247,7 @@ apm_suspend(int state)
bufq_quiesce();
s = splhigh();
- disable_intr();
+ intr_disable();
cold = 2;
config_suspend_all(DVACT_SUSPEND);
suspend_randomness();
@@ -272,7 +272,7 @@ apm_suspend(int state)
config_suspend_all(DVACT_RESUME);
cold = 0;
- enable_intr();
+ intr_enable();
splx(s);
resume_randomness(NULL, 0); /* force RNG upper level reseed */
Index: arch/i386/i386/cpu.c
===================================================================
RCS file: /cvs/src/sys/arch/i386/i386/cpu.c,v
retrieving revision 1.93
diff -u -p -r1.93 cpu.c
--- arch/i386/i386/cpu.c 22 Jun 2018 13:21:14 -0000 1.93
+++ arch/i386/i386/cpu.c 27 Jul 2018 23:10:46 -0000
@@ -705,7 +705,7 @@ cpu_hatch(void *v)
s = splhigh(); /* XXX prevent softints from running here.. */
lapic_tpr = 0;
- enable_intr();
+ intr_enable();
if (mp_verbose)
printf("%s: CPU at apid %ld running\n",
ci->ci_dev->dv_xname, ci->ci_cpuid);
Index: arch/i386/i386/hibernate_machdep.c
===================================================================
RCS file: /cvs/src/sys/arch/i386/i386/hibernate_machdep.c,v
retrieving revision 1.54
diff -u -p -r1.54 hibernate_machdep.c
--- arch/i386/i386/hibernate_machdep.c 4 Jul 2018 02:05:06 -0000 1.54
+++ arch/i386/i386/hibernate_machdep.c 27 Jul 2018 23:10:46 -0000
@@ -387,13 +387,13 @@ hibernate_inflate_skip(union hibernate_i
void
hibernate_enable_intr_machdep(void)
{
- enable_intr();
+ intr_enable();
}
void
hibernate_disable_intr_machdep(void)
{
- disable_intr();
+ intr_disable();
}
#ifdef MULTIPROCESSOR
Index: arch/i386/i386/i686_mem.c
===================================================================
RCS file: /cvs/src/sys/arch/i386/i386/i686_mem.c,v
retrieving revision 1.18
diff -u -p -r1.18 i686_mem.c
--- arch/i386/i386/i686_mem.c 26 Apr 2016 15:27:32 -0000 1.18
+++ arch/i386/i386/i686_mem.c 27 Jul 2018 23:10:46 -0000
@@ -275,12 +275,14 @@ mrt2mtrr(u_int64_t flags)
void
mrstore(struct mem_range_softc *sc)
{
- disable_intr(); /* disable interrupts */
+ u_long s;
+
+ s = intr_disable(); /* disable interrupts */
#ifdef MULTIPROCESSOR
i386_broadcast_ipi(I386_IPI_MTRR);
#endif
mrstoreone(sc);
- enable_intr();
+ intr_restore(s);
}
/*
@@ -618,7 +620,9 @@ mrinit_cpu(struct mem_range_softc *sc)
void
mrreload_cpu(struct mem_range_softc *sc)
{
- disable_intr();
+ u_long s;
+
+ s = intr_disable();
mrstoreone(sc); /* set MTRRs to match BSP */
- enable_intr();
+ intr_restore(s);
}
Index: arch/i386/i386/ipifuncs.c
===================================================================
RCS file: /cvs/src/sys/arch/i386/i386/ipifuncs.c,v
retrieving revision 1.30
diff -u -p -r1.30 ipifuncs.c
--- arch/i386/i386/ipifuncs.c 4 Dec 2017 21:12:41 -0000 1.30
+++ arch/i386/i386/ipifuncs.c 27 Jul 2018 23:10:46 -0000
@@ -116,7 +116,7 @@ i386_ipi_halt(struct cpu_info *ci)
KASSERT(!_kernel_lock_held());
npxsave_cpu(ci, 1);
- disable_intr();
+ intr_disable();
lapic_disable();
wbinvd();
ci->ci_flags &= ~CPUF_RUNNING;
Index: arch/i386/i386/k6_mem.c
===================================================================
RCS file: /cvs/src/sys/arch/i386/i386/k6_mem.c,v
retrieving revision 1.12
diff -u -p -r1.12 k6_mem.c
--- arch/i386/i386/k6_mem.c 8 Sep 2015 04:28:34 -0000 1.12
+++ arch/i386/i386/k6_mem.c 27 Jul 2018 23:10:46 -0000
@@ -130,6 +130,7 @@ k6_mrset(struct mem_range_softc *sc, str
u_int64_t reg;
u_int32_t mtrr;
int error, d;
+ u_long s;
switch (*arg) {
case MEMRANGE_SET_UPDATE:
@@ -163,14 +164,14 @@ k6_mrset(struct mem_range_softc *sc, str
out:
- disable_intr();
+ s = intr_disable();
wbinvd();
reg = rdmsr(UWCCR);
reg &= ~(0xffffffff << (32 * d));
reg |= mtrr << (32 * d);
wrmsr(UWCCR, reg);
wbinvd();
- enable_intr();
+ intr_restore(s);
return 0;
}
@@ -184,17 +185,18 @@ k6_mrinit_cpu(struct mem_range_softc *sc
u_int64_t reg;
u_int32_t mtrr;
int d;
+ u_long s;
for (d = 0; d < sc->mr_ndesc; d++) {
k6_mrmake(&sc->mr_desc[d], &mtrr);
- disable_intr();
+ s = intr_disable();
wbinvd();
reg = rdmsr(UWCCR);
reg &= ~(0xffffffff << (32 * d));
reg |= mtrr << (32 * d);
wrmsr(UWCCR, reg);
wbinvd();
- enable_intr();
+ intr_restore(s);
}
}
Index: arch/i386/i386/lapic.c
===================================================================
RCS file: /cvs/src/sys/arch/i386/i386/lapic.c,v
retrieving revision 1.46
diff -u -p -r1.46 lapic.c
--- arch/i386/i386/lapic.c 20 Apr 2018 07:27:54 -0000 1.46
+++ arch/i386/i386/lapic.c 27 Jul 2018 23:10:46 -0000
@@ -77,11 +77,12 @@ void lapic_map(paddr_t);
void
lapic_map(paddr_t lapic_base)
{
- int s;
vaddr_t va = (vaddr_t)&local_apic;
+ u_long s;
+ int tpr;
- disable_intr();
- s = lapic_tpr;
+ s = intr_disable();
+ tpr = lapic_tpr;
/*
* Map local apic. If we have a local apic, it's safe to assume
@@ -103,8 +104,8 @@ lapic_map(paddr_t lapic_base)
cpu_init_first();
#endif
- lapic_tpr = s;
- enable_intr();
+ lapic_tpr = tpr;
+ intr_restore(s);
}
/*
@@ -316,7 +317,8 @@ lapic_calibrate_timer(struct cpu_info *c
{
unsigned int startapic, endapic;
u_int64_t dtick, dapic, tmp;
- int i, ef = read_eflags();
+ u_long s;
+ int i;
if (mp_verbose)
printf("%s: calibrating local timer\n", ci->ci_dev->dv_xname);
@@ -329,7 +331,7 @@ lapic_calibrate_timer(struct cpu_info *c
i82489_writereg(LAPIC_DCR_TIMER, LAPIC_DCRT_DIV1);
i82489_writereg(LAPIC_ICR_TIMER, 0x80000000);
- disable_intr();
+ s = intr_disable();
/* wait for current cycle to finish */
wait_next_cycle();
@@ -341,7 +343,8 @@ lapic_calibrate_timer(struct cpu_info *c
wait_next_cycle();
endapic = lapic_gettick();
- write_eflags(ef);
+
+ intr_restore(s);
dtick = hz * TIMER_DIV(hz);
dapic = startapic-endapic;
Index: arch/i386/i386/longrun.c
===================================================================
RCS file: /cvs/src/sys/arch/i386/i386/longrun.c,v
retrieving revision 1.16
diff -u -p -r1.16 longrun.c
--- arch/i386/i386/longrun.c 14 Sep 2014 14:17:23 -0000 1.16
+++ arch/i386/i386/longrun.c 27 Jul 2018 23:10:46 -0000
@@ -74,13 +74,12 @@ longrun_init(void)
void
longrun_update(void *arg)
{
- uint32_t eflags, regs[4];
+ uint32_t regs[4];
+ u_long s;
- eflags = read_eflags();
- disable_intr();
+ s = intr_disable();
cpuid(0x80860007, regs);
- enable_intr();
- write_eflags(eflags);
+ intr_restore(s);
cpuspeed = regs[0];
@@ -98,16 +97,16 @@ longrun_update(void *arg)
void
longrun_setperf(int high)
{
- uint32_t eflags, mode;
union msrinfo msrinfo;
+ uint32_t mode;
+ u_long s;
if (high >= 50)
mode = 1; /* power */
else
mode = 0; /* battery */
- eflags = read_eflags();
- disable_intr();
+ s = intr_disable();
msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
msrinfo.regs[0] = LONGRUN_MODE_WRITE(msrinfo.regs[0], 0); /* low */
@@ -118,8 +117,7 @@ longrun_setperf(int high)
msrinfo.regs[0] = (msrinfo.regs[0] & ~0x01) | mode;
wrmsr(MSR_TMx86_LONGRUN_FLAGS, msrinfo.msr);
- enable_intr();
- write_eflags(eflags);
+ intr_restore(s);
longrun_update(NULL);
}
Index: arch/i386/i386/machdep.c
===================================================================
RCS file: /cvs/src/sys/arch/i386/i386/machdep.c,v
retrieving revision 1.621
diff -u -p -r1.621 machdep.c
--- arch/i386/i386/machdep.c 24 Jul 2018 17:31:23 -0000 1.621
+++ arch/i386/i386/machdep.c 27 Jul 2018 23:10:46 -0000
@@ -3418,7 +3418,7 @@ cpu_reset(void)
{
struct region_descriptor region;
- disable_intr();
+ intr_disable();
if (cpuresetfn)
(*cpuresetfn)();
Index: arch/i386/i386/powernow-k7.c
===================================================================
RCS file: /cvs/src/sys/arch/i386/i386/powernow-k7.c,v
retrieving revision 1.42
diff -u -p -r1.42 powernow-k7.c
--- arch/i386/i386/powernow-k7.c 4 Jul 2018 02:06:15 -0000 1.42
+++ arch/i386/i386/powernow-k7.c 27 Jul 2018 23:10:46 -0000
@@ -154,6 +154,7 @@ k7_powernow_setperf(int level)
int cvid, cfid, vid = 0, fid = 0;
uint64_t status, ctl;
struct k7pnow_cpu_state * cstate;
+ u_long s;
cstate = k7pnow_current_state;
@@ -183,7 +184,7 @@ k7_powernow_setperf(int level)
ctl |= PN7_CTR_SGTC(cstate->sgtc);
if (cstate->flags & PN7_FLAG_ERRATA_A0)
- disable_intr();
+ s = intr_disable();
if (k7pnow_fid_to_mult[fid] < k7pnow_fid_to_mult[cfid]) {
wrmsr(MSR_AMDK7_FIDVID_CTL, ctl | PN7_CTR_FIDC);
@@ -196,7 +197,7 @@ k7_powernow_setperf(int level)
}
if (cstate->flags & PN7_FLAG_ERRATA_A0)
- enable_intr();
+ intr_restore(s);
status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
cfid = PN7_STA_CFID(status);
Index: arch/i386/include/cpufunc.h
===================================================================
RCS file: /cvs/src/sys/arch/i386/include/cpufunc.h,v
retrieving revision 1.29
diff -u -p -r1.29 cpufunc.h
--- arch/i386/include/cpufunc.h 30 Jun 2018 10:16:35 -0000 1.29
+++ arch/i386/include/cpufunc.h 27 Jul 2018 23:10:46 -0000
@@ -56,8 +56,6 @@ static __inline u_int rcr3(void);
static __inline void lcr4(u_int);
static __inline u_int rcr4(void);
static __inline void tlbflush(void);
-static __inline void disable_intr(void);
-static __inline void enable_intr(void);
static __inline u_int read_eflags(void);
static __inline void write_eflags(u_int);
static __inline void wbinvd(void);
@@ -156,18 +154,6 @@ void setidt(int idx, /*XXX*/caddr_t func
/* XXXX ought to be in psl.h with spl() functions */
-static __inline void
-disable_intr(void)
-{
- __asm volatile("cli");
-}
-
-static __inline void
-enable_intr(void)
-{
- __asm volatile("sti");
-}
-
static __inline u_int
read_eflags(void)
{
@@ -186,7 +172,7 @@ write_eflags(u_int ef)
static inline void
intr_enable(void)
{
- enable_intr();
+ __asm volatile("sti");
}
static inline u_long
@@ -195,7 +181,7 @@ intr_disable(void)
u_long ef;
ef = read_eflags();
- disable_intr();
+ __asm volatile("cli");
return (ef);
}
Index: arch/i386/isa/clock.c
===================================================================
RCS file: /cvs/src/sys/arch/i386/isa/clock.c,v
retrieving revision 1.52
diff -u -p -r1.52 clock.c
--- arch/i386/isa/clock.c 8 Sep 2017 05:36:51 -0000 1.52
+++ arch/i386/isa/clock.c 27 Jul 2018 23:10:46 -0000
@@ -244,6 +244,7 @@ rtcintr(void *arg)
int
gettick(void)
{
+ u_long s;
if (clock_broken_latch) {
int v1, v2, v3;
@@ -254,7 +255,7 @@ gettick(void)
* CPUs don't do MP anyway.
*/
- disable_intr();
+ s = intr_disable();
v1 = inb(IO_TIMER1 + TIMER_CNTR0);
v1 |= inb(IO_TIMER1 + TIMER_CNTR0) << 8;
@@ -263,7 +264,7 @@ gettick(void)
v3 = inb(IO_TIMER1 + TIMER_CNTR0);
v3 |= inb(IO_TIMER1 + TIMER_CNTR0) << 8;
- enable_intr();
+ intr_restore(s);
if (v1 >= v2 && v2 >= v3 && v1 - v3 < 0x200)
return (v2);
@@ -298,17 +299,15 @@ gettick(void)
return (v3);
} else {
u_char lo, hi;
- u_long ef;
mtx_enter(&timer_mutex);
- ef = read_eflags();
- disable_intr();
+ s = intr_disable();
/* Select counter 0 and latch it. */
outb(IO_TIMER1 + TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
lo = inb(IO_TIMER1 + TIMER_CNTR0);
hi = inb(IO_TIMER1 + TIMER_CNTR0);
- write_eflags(ef);
+ intr_restore(s);
mtx_leave(&timer_mutex);
return ((hi << 8) | lo);
}
@@ -750,10 +749,9 @@ i8254_get_timecount(struct timecounter *
{
u_char hi, lo;
u_int count;
- u_long ef;
+ u_long s;
- ef = read_eflags();
- disable_intr();
+ s = intr_disable();
outb(IO_TIMER1 + TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
lo = inb(IO_TIMER1 + TIMER_CNTR0);
@@ -767,7 +765,8 @@ i8254_get_timecount(struct timecounter *
}
i8254_lastcount = count;
count += i8254_offset;
- write_eflags(ef);
+
+ intr_restore(s);
return (count);
}
Index: arch/i386/isa/joy.c
===================================================================
RCS file: /cvs/src/sys/arch/i386/isa/joy.c,v
retrieving revision 1.15
diff -u -p -r1.15 joy.c
--- arch/i386/isa/joy.c 10 Feb 2015 21:58:16 -0000 1.15
+++ arch/i386/isa/joy.c 27 Jul 2018 23:10:46 -0000
@@ -97,8 +97,9 @@ joyread(dev_t dev, struct uio *uio, int
int port = sc->port;
int i, t0, t1;
int state = 0, x = 0, y = 0;
+ u_long s;
- disable_intr();
+ s = intr_disable();
outb(port, 0xff);
t0 = joy_get_tick();
t1 = t0;
@@ -117,7 +118,7 @@ joyread(dev_t dev, struct uio *uio, int
if (x && y)
break;
}
- enable_intr();
+ intr_restore(s);
c.x = x ? sc->x_off[JOYPART(dev)] + TICKS2USEC(t0 - x) : 0x80000000;
c.y = y ? sc->y_off[JOYPART(dev)] + TICKS2USEC(t0 - y) : 0x80000000;
state >>= 4;
Index: arch/i386/isa/npx.c
===================================================================
RCS file: /cvs/src/sys/arch/i386/isa/npx.c,v
retrieving revision 1.69
diff -u -p -r1.69 npx.c
--- arch/i386/isa/npx.c 11 Apr 2018 15:44:08 -0000 1.69
+++ arch/i386/isa/npx.c 27 Jul 2018 23:10:46 -0000
@@ -275,7 +275,7 @@ npxprobe(struct device *parent, void *ma
struct isa_attach_args *ia = aux;
int irq;
int result;
- u_long save_eflags;
+ u_long s;
unsigned save_imen;
struct gate_descriptor save_idt_npxintr;
struct gate_descriptor save_idt_npxtrap;
@@ -297,8 +297,7 @@ npxprobe(struct device *parent, void *ma
* won't need to do so much here.
*/
irq = NRSVIDT + ia->ia_irq;
- save_eflags = read_eflags();
- disable_intr();
+ s = intr_disable();
save_idt_npxintr = idt[irq];
save_idt_npxtrap = idt[16];
setgate(&idt[irq], probeintr, 0, SDT_SYS386IGT, SEL_KPL, GICODE_SEL);
@@ -320,16 +319,16 @@ npxprobe(struct device *parent, void *ma
* We have to turn off the CR0_EM bit temporarily while probing.
*/
lcr0(rcr0() & ~(CR0_EM|CR0_TS));
- enable_intr();
+ intr_restore(s);
result = npxprobe1(ia);
- disable_intr();
+ s = intr_disable();
lcr0(rcr0() | (CR0_EM|CR0_TS));
imen = save_imen;
SET_ICUS();
idt[irq] = save_idt_npxintr;
idt[16] = save_idt_npxtrap;
- write_eflags(save_eflags);
+ intr_restore(s);
return (result);
}
Index: arch/i386/pci/elan520.c
===================================================================
RCS file: /cvs/src/sys/arch/i386/pci/elan520.c,v
retrieving revision 1.21
diff -u -p -r1.21 elan520.c
--- arch/i386/pci/elan520.c 10 Dec 2014 12:27:56 -0000 1.21
+++ arch/i386/pci/elan520.c 27 Jul 2018 23:10:46 -0000
@@ -345,8 +345,8 @@ elansc_update_cpuspeed(void)
void
elansc_setperf(int level)
{
- uint32_t eflags;
uint8_t cpuctl, speed;
+ u_long s;
level = (level > 50) ? 100 : 0;
@@ -356,12 +356,10 @@ elansc_setperf(int level)
if ((cpuctl & CPUCTL_CPU_CLK_SPD_MASK) == speed)
return;
- eflags = read_eflags();
- disable_intr();
+ s = intr_disable();
bus_space_write_1(elansc->sc_memt, elansc->sc_memh, MMCR_CPUCTL,
(cpuctl & ~CPUCTL_CPU_CLK_SPD_MASK) | speed);
- enable_intr();
- write_eflags(eflags);
+ intr_restore(s);
elansc_update_cpuspeed();
}
Index: dev/isa/gus.c
===================================================================
RCS file: /cvs/src/sys/dev/isa/gus.c,v
retrieving revision 1.46
diff -u -p -r1.46 gus.c
--- dev/isa/gus.c 4 May 2017 15:19:01 -0000 1.46
+++ dev/isa/gus.c 27 Jul 2018 23:10:47 -0000
@@ -3198,6 +3198,7 @@ gus_subattach(struct gus_softc *sc, stru
int i;
bus_space_tag_t iot;
unsigned char c,d,m;
+ u_long s;
iot = sc->sc_iot;
@@ -3244,7 +3245,7 @@ gus_subattach(struct gus_softc *sc, stru
* The order of these operations is very magical.
*/
- disable_intr(); /* XXX needed? */
+ s = intr_disable(); /* XXX needed? */
bus_space_write_1(iot, sc->sc_ioh1, GUS_REG_CONTROL, GUS_REG_IRQCTL);
bus_space_write_1(iot, sc->sc_ioh1, GUS_MIX_CONTROL, m);
@@ -3274,7 +3275,7 @@ gus_subattach(struct gus_softc *sc, stru
(m | GUSMASK_LATCHES) & ~(GUSMASK_LINE_OUT|GUSMASK_LINE_IN));
bus_space_write_1(iot, sc->sc_ioh2, GUS_VOICE_SELECT, 0x00);
- enable_intr();
+ intr_restore(s);
sc->sc_mixcontrol =
(m | GUSMASK_LATCHES) & ~(GUSMASK_LINE_OUT|GUSMASK_LINE_IN);
>
>
> Index: arch/amd64/amd64/amd64_mem.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/amd64/amd64/amd64_mem.c,v
> retrieving revision 1.13
> diff -u -p -r1.13 amd64_mem.c
> --- arch/amd64/amd64/amd64_mem.c 26 Apr 2016 15:27:32 -0000 1.13
> +++ arch/amd64/amd64/amd64_mem.c 24 Jul 2018 21:55:40 -0000
> @@ -274,12 +274,14 @@ mrt2mtrr(u_int64_t flags)
> void
> mrstore(struct mem_range_softc *sc)
> {
> - disable_intr(); /* disable interrupts */
> + u_long s;
> +
> + s = intr_disable();
> #ifdef MULTIPROCESSOR
> x86_broadcast_ipi(X86_IPI_MTRR);
> #endif
> mrstoreone(sc);
> - enable_intr();
> + intr_restore(s);
> }
>
> /*
> @@ -616,7 +618,9 @@ mrinit_cpu(struct mem_range_softc *sc)
> void
> mrreload_cpu(struct mem_range_softc *sc)
> {
> - disable_intr();
> + u_long s;
> +
> + s = intr_disable();
> mrstoreone(sc); /* set MTRRs to match BSP */
> - enable_intr();
> + intr_restore(s);
> }
> Index: arch/amd64/amd64/cpu.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/amd64/amd64/cpu.c,v
> retrieving revision 1.125
> diff -u -p -r1.125 cpu.c
> --- arch/amd64/amd64/cpu.c 12 Jul 2018 14:11:11 -0000 1.125
> +++ arch/amd64/amd64/cpu.c 24 Jul 2018 21:55:40 -0000
> @@ -800,7 +800,7 @@ cpu_hatch(void *v)
>
> s = splhigh();
> lcr8(0);
> - enable_intr();
> + intr_enable();
>
> nanouptime(&ci->ci_schedstate.spc_runtime);
> splx(s);
> Index: arch/amd64/amd64/hibernate_machdep.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/amd64/amd64/hibernate_machdep.c,v
> retrieving revision 1.44
> diff -u -p -r1.44 hibernate_machdep.c
> --- arch/amd64/amd64/hibernate_machdep.c 4 Jul 2018 01:41:56 -0000
> 1.44
> +++ arch/amd64/amd64/hibernate_machdep.c 24 Jul 2018 21:55:40 -0000
> @@ -440,13 +440,13 @@ hibernate_inflate_skip(union hibernate_i
> void
> hibernate_enable_intr_machdep(void)
> {
> - enable_intr();
> + intr_enable();
> }
>
> void
> hibernate_disable_intr_machdep(void)
> {
> - disable_intr();
> + intr_disable();
> }
>
> #ifdef MULTIPROCESSOR
> Index: arch/amd64/amd64/i8259.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/amd64/amd64/i8259.c,v
> retrieving revision 1.10
> diff -u -p -r1.10 i8259.c
> --- arch/amd64/amd64/i8259.c 14 Oct 2017 04:44:43 -0000 1.10
> +++ arch/amd64/amd64/i8259.c 24 Jul 2018 21:55:40 -0000
> @@ -162,8 +162,9 @@ i8259_hwunmask(struct pic *pic, int pin)
> {
> unsigned port;
> u_int8_t byte;
> + u_long s;
>
> - disable_intr(); /* XXX */
> + s = intr_disable();
> i8259_imen &= ~(1 << pin);
> #ifdef PIC_MASKDELAY
> delay(10);
> @@ -176,7 +177,7 @@ i8259_hwunmask(struct pic *pic, int pin)
> byte = i8259_imen & 0xff;
> }
> outb(port, byte);
> - enable_intr();
> + intr_restore(s);
> }
>
> static void
> Index: arch/amd64/amd64/ipifuncs.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/amd64/amd64/ipifuncs.c,v
> retrieving revision 1.31
> diff -u -p -r1.31 ipifuncs.c
> --- arch/amd64/amd64/ipifuncs.c 5 Jun 2018 06:39:10 -0000 1.31
> +++ arch/amd64/amd64/ipifuncs.c 24 Jul 2018 21:55:40 -0000
> @@ -111,7 +111,7 @@ x86_64_ipi_halt(struct cpu_info *ci)
> SCHED_ASSERT_UNLOCKED();
> KASSERT(!_kernel_lock_held());
>
> - disable_intr();
> + intr_disable();
> lapic_disable();
> wbinvd();
> ci->ci_flags &= ~CPUF_RUNNING;
> Index: arch/amd64/amd64/lapic.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/amd64/amd64/lapic.c,v
> retrieving revision 1.51
> diff -u -p -r1.51 lapic.c
> --- arch/amd64/amd64/lapic.c 20 Apr 2018 07:27:54 -0000 1.51
> +++ arch/amd64/amd64/lapic.c 24 Jul 2018 21:55:40 -0000
> @@ -174,13 +174,14 @@ lapic_cpu_number(void)
> void
> lapic_map(paddr_t lapic_base)
> {
> - int s;
> pt_entry_t *pte;
> vaddr_t va;
> u_int64_t msr;
> + u_long s;
> + int tpr;
>
> - disable_intr();
> - s = lapic_tpr;
> + s = intr_disable();
> + tpr = lapic_tpr;
>
> msr = rdmsr(MSR_APICBASE);
>
> @@ -208,7 +209,7 @@ lapic_map(paddr_t lapic_base)
> x2apic_enabled = 1;
> codepatch_call(CPTAG_EOI, &x2apic_eoi);
>
> - lapic_writereg(LAPIC_TPRI, s);
> + lapic_writereg(LAPIC_TPRI, tpr);
> va = (vaddr_t)&local_apic;
> } else {
> /*
> @@ -226,7 +227,7 @@ lapic_map(paddr_t lapic_base)
> *pte = lapic_base | PG_RW | PG_V | PG_N | PG_G | pg_nx;
> invlpg(va);
>
> - lapic_tpr = s;
> + lapic_tpr = tpr;
> }
>
> /*
> @@ -240,7 +241,7 @@ lapic_map(paddr_t lapic_base)
> DPRINTF("%s: entered lapic page va 0x%llx pa 0x%llx\n", __func__,
> (uint64_t)va, (uint64_t)lapic_base);
>
> - enable_intr();
> + intr_restore(s);
> }
>
> /*
> @@ -479,7 +480,7 @@ lapic_calibrate_timer(struct cpu_info *c
> {
> unsigned int startapic, endapic;
> u_int64_t dtick, dapic, tmp;
> - long rf = read_rflags();
> + u_long s;
> int i;
>
> if (mp_verbose)
> @@ -493,7 +494,7 @@ lapic_calibrate_timer(struct cpu_info *c
> lapic_writereg(LAPIC_DCR_TIMER, LAPIC_DCRT_DIV1);
> lapic_writereg(LAPIC_ICR_TIMER, 0x80000000);
>
> - disable_intr();
> + s = intr_disable();
>
> /* wait for current cycle to finish */
> wait_next_cycle();
> @@ -505,7 +506,8 @@ lapic_calibrate_timer(struct cpu_info *c
> wait_next_cycle();
>
> endapic = lapic_gettick();
> - write_rflags(rf);
> +
> + intr_restore(s);
>
> dtick = hz * rtclock_tval;
> dapic = startapic-endapic;
> Index: arch/amd64/amd64/machdep.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/amd64/amd64/machdep.c,v
> retrieving revision 1.248
> diff -u -p -r1.248 machdep.c
> --- arch/amd64/amd64/machdep.c 12 Jul 2018 14:11:11 -0000 1.248
> +++ arch/amd64/amd64/machdep.c 24 Jul 2018 21:55:40 -0000
> @@ -1705,7 +1705,7 @@ init_x86_64(paddr_t first_avail)
>
> softintr_init();
> splraise(IPL_IPI);
> - enable_intr();
> + intr_enable();
>
> #ifdef DDB
> db_machine_init();
> @@ -1718,8 +1718,7 @@ init_x86_64(paddr_t first_avail)
> void
> cpu_reset(void)
> {
> -
> - disable_intr();
> + intr_disable();
>
> if (cpuresetfn)
> (*cpuresetfn)();
> Index: arch/amd64/amd64/tsc.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/amd64/amd64/tsc.c,v
> retrieving revision 1.9
> diff -u -p -r1.9 tsc.c
> --- arch/amd64/amd64/tsc.c 8 Apr 2018 18:26:29 -0000 1.9
> +++ arch/amd64/amd64/tsc.c 24 Jul 2018 21:55:40 -0000
> @@ -120,7 +120,7 @@ uint64_t
> measure_tsc_freq(struct timecounter *tc)
> {
> uint64_t count1, count2, frequency, min_freq, tsc1, tsc2;
> - u_long ef;
> + u_long s;
> int delay_usec, i, err1, err2, usec, success = 0;
>
> /* warmup the timers */
> @@ -133,14 +133,13 @@ measure_tsc_freq(struct timecounter *tc)
>
> delay_usec = 100000;
> for (i = 0; i < 3; i++) {
> - ef = read_rflags();
> - disable_intr();
> + s = intr_disable();
>
> err1 = get_tsc_and_timecount(tc, &tsc1, &count1);
> delay(delay_usec);
> err2 = get_tsc_and_timecount(tc, &tsc2, &count2);
>
> - write_rflags(ef);
> + intr_restore(s);
>
> if (err1 || err2)
> continue;
> Index: arch/amd64/amd64/vmm.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/amd64/amd64/vmm.c,v
> retrieving revision 1.216
> diff -u -p -r1.216 vmm.c
> --- arch/amd64/amd64/vmm.c 12 Jul 2018 10:16:41 -0000 1.216
> +++ arch/amd64/amd64/vmm.c 24 Jul 2018 21:55:40 -0000
> @@ -3905,6 +3905,7 @@ vcpu_run_vmx(struct vcpu *vcpu, struct v
> struct vmx_invvpid_descriptor vid;
> uint64_t eii, procbased, int_st;
> uint16_t irq;
> + u_long s;
>
> resume = 0;
> irq = vrp->vrp_irq;
> @@ -4099,9 +4100,9 @@ vcpu_run_vmx(struct vcpu *vcpu, struct v
> #endif /* VMM_DEBUG */
>
> /* Disable interrupts and save the current host FPU state. */
> - disable_intr();
> + s = intr_disable();
> if ((ret = vmm_fpurestore(vcpu))) {
> - enable_intr();
> + intr_restore(s);
> break;
> }
>
> @@ -4116,7 +4117,7 @@ vcpu_run_vmx(struct vcpu *vcpu, struct v
> */
> vmm_fpusave(vcpu);
>
> - enable_intr();
> + intr_restore(s);
>
> exit_reason = VM_EXIT_NONE;
> if (ret == 0) {
> Index: arch/amd64/include/cpufunc.h
> ===================================================================
> RCS file: /cvs/src/sys/arch/amd64/include/cpufunc.h,v
> retrieving revision 1.29
> diff -u -p -r1.29 cpufunc.h
> --- arch/amd64/include/cpufunc.h 24 Jul 2018 14:49:44 -0000 1.29
> +++ arch/amd64/include/cpufunc.h 24 Jul 2018 21:55:40 -0000
> @@ -152,18 +152,6 @@ void setidt(int idx, /*XXX*/caddr_t func
>
> /* XXXX ought to be in psl.h with spl() functions */
>
> -static __inline void
> -disable_intr(void)
> -{
> - __asm volatile("cli");
> -}
> -
> -static __inline void
> -enable_intr(void)
> -{
> - __asm volatile("sti");
> -}
> -
> static __inline u_long
> read_rflags(void)
> {
> @@ -182,7 +170,7 @@ write_rflags(u_long ef)
> static __inline void
> intr_enable(void)
> {
> - enable_intr();
> + __asm volatile("sti");
> }
>
> static __inline u_long
> @@ -191,7 +179,7 @@ intr_disable(void)
> u_long ef;
>
> ef = read_rflags();
> - disable_intr();
> + __asm volatile("cli");
> return (ef);
> }
>
> Index: arch/amd64/isa/clock.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/amd64/isa/clock.c,v
> retrieving revision 1.27
> diff -u -p -r1.27 clock.c
> --- arch/amd64/isa/clock.c 9 Jul 2018 19:38:33 -0000 1.27
> +++ arch/amd64/isa/clock.c 24 Jul 2018 21:55:40 -0000
> @@ -201,18 +201,17 @@ rtcintr(void *arg)
> int
> gettick(void)
> {
> - u_long ef;
> + u_long s;
> u_char lo, hi;
>
> /* Don't want someone screwing with the counter while we're here. */
> mtx_enter(&timer_mutex);
> - ef = read_rflags();
> - disable_intr();
> + s = intr_disable();
> /* Select counter 0 and latch it. */
> outb(IO_TIMER1+TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
> lo = inb(IO_TIMER1+TIMER_CNTR0);
> hi = inb(IO_TIMER1+TIMER_CNTR0);
> - write_rflags(ef);
> + intr_restore(s);
> mtx_leave(&timer_mutex);
> return ((hi << 8) | lo);
> }
> @@ -632,10 +631,9 @@ i8254_get_timecount(struct timecounter *
> {
> u_char hi, lo;
> u_int count;
> - u_long ef;
> + u_long s;
>
> - ef = read_rflags();
> - disable_intr();
> + s = intr_disable();
>
> outb(IO_TIMER1+TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
> lo = inb(IO_TIMER1+TIMER_CNTR0);
> @@ -649,7 +647,8 @@ i8254_get_timecount(struct timecounter *
> }
> i8254_lastcount = count;
> count += i8254_offset;
> - write_rflags(ef);
> +
> + intr_restore(s);
>
> return (count);
> }
> Index: dev/pci/drm/drm_linux.h
> ===================================================================
> RCS file: /cvs/src/sys/dev/pci/drm/drm_linux.h,v
> retrieving revision 1.89
> diff -u -p -r1.89 drm_linux.h
> --- dev/pci/drm/drm_linux.h 25 Jun 2018 22:29:16 -0000 1.89
> +++ dev/pci/drm/drm_linux.h 24 Jul 2018 21:55:41 -0000
> @@ -898,8 +898,8 @@ void flush_delayed_work(struct delayed_w
> typedef void *async_cookie_t;
> #define async_schedule(func, data) (func)((data), NULL)
>
> -#define local_irq_disable() disable_intr()
> -#define local_irq_enable() enable_intr()
> +#define local_irq_disable() intr_disable()
> +#define local_irq_enable() intr_enable()
>
> #define setup_timer(x, y, z) timeout_set((x), (void (*)(void *))(y), (void
> *)(z))
> #define mod_timer(x, y) timeout_add((x), (y - jiffies))
>
>
