Diff below switches to the MI equivalent and kills the MD-specific
API.
ok?
Index: arch/amd64/amd64/amd64_mem.c
===================================================================
RCS file: /cvs/src/sys/arch/amd64/amd64/amd64_mem.c,v
retrieving revision 1.13
diff -u -p -r1.13 amd64_mem.c
--- arch/amd64/amd64/amd64_mem.c 26 Apr 2016 15:27:32 -0000 1.13
+++ arch/amd64/amd64/amd64_mem.c 24 Jul 2018 21:55:40 -0000
@@ -274,12 +274,14 @@ mrt2mtrr(u_int64_t flags)
void
mrstore(struct mem_range_softc *sc)
{
- disable_intr(); /* disable interrupts */
+ u_long s;
+
+ s = intr_disable();
#ifdef MULTIPROCESSOR
x86_broadcast_ipi(X86_IPI_MTRR);
#endif
mrstoreone(sc);
- enable_intr();
+ intr_restore(s);
}
/*
@@ -616,7 +618,9 @@ mrinit_cpu(struct mem_range_softc *sc)
void
mrreload_cpu(struct mem_range_softc *sc)
{
- disable_intr();
+ u_long s;
+
+ s = intr_disable();
mrstoreone(sc); /* set MTRRs to match BSP */
- enable_intr();
+ intr_restore(s);
}
Index: arch/amd64/amd64/cpu.c
===================================================================
RCS file: /cvs/src/sys/arch/amd64/amd64/cpu.c,v
retrieving revision 1.125
diff -u -p -r1.125 cpu.c
--- arch/amd64/amd64/cpu.c 12 Jul 2018 14:11:11 -0000 1.125
+++ arch/amd64/amd64/cpu.c 24 Jul 2018 21:55:40 -0000
@@ -800,7 +800,7 @@ cpu_hatch(void *v)
s = splhigh();
lcr8(0);
- enable_intr();
+ intr_enable();
nanouptime(&ci->ci_schedstate.spc_runtime);
splx(s);
Index: arch/amd64/amd64/hibernate_machdep.c
===================================================================
RCS file: /cvs/src/sys/arch/amd64/amd64/hibernate_machdep.c,v
retrieving revision 1.44
diff -u -p -r1.44 hibernate_machdep.c
--- arch/amd64/amd64/hibernate_machdep.c 4 Jul 2018 01:41:56 -0000
1.44
+++ arch/amd64/amd64/hibernate_machdep.c 24 Jul 2018 21:55:40 -0000
@@ -440,13 +440,13 @@ hibernate_inflate_skip(union hibernate_i
void
hibernate_enable_intr_machdep(void)
{
- enable_intr();
+ intr_enable();
}
void
hibernate_disable_intr_machdep(void)
{
- disable_intr();
+ intr_disable();
}
#ifdef MULTIPROCESSOR
Index: arch/amd64/amd64/i8259.c
===================================================================
RCS file: /cvs/src/sys/arch/amd64/amd64/i8259.c,v
retrieving revision 1.10
diff -u -p -r1.10 i8259.c
--- arch/amd64/amd64/i8259.c 14 Oct 2017 04:44:43 -0000 1.10
+++ arch/amd64/amd64/i8259.c 24 Jul 2018 21:55:40 -0000
@@ -162,8 +162,9 @@ i8259_hwunmask(struct pic *pic, int pin)
{
unsigned port;
u_int8_t byte;
+ u_long s;
- disable_intr(); /* XXX */
+ s = intr_disable();
i8259_imen &= ~(1 << pin);
#ifdef PIC_MASKDELAY
delay(10);
@@ -176,7 +177,7 @@ i8259_hwunmask(struct pic *pic, int pin)
byte = i8259_imen & 0xff;
}
outb(port, byte);
- enable_intr();
+ intr_restore(s);
}
static void
Index: arch/amd64/amd64/ipifuncs.c
===================================================================
RCS file: /cvs/src/sys/arch/amd64/amd64/ipifuncs.c,v
retrieving revision 1.31
diff -u -p -r1.31 ipifuncs.c
--- arch/amd64/amd64/ipifuncs.c 5 Jun 2018 06:39:10 -0000 1.31
+++ arch/amd64/amd64/ipifuncs.c 24 Jul 2018 21:55:40 -0000
@@ -111,7 +111,7 @@ x86_64_ipi_halt(struct cpu_info *ci)
SCHED_ASSERT_UNLOCKED();
KASSERT(!_kernel_lock_held());
- disable_intr();
+ intr_disable();
lapic_disable();
wbinvd();
ci->ci_flags &= ~CPUF_RUNNING;
Index: arch/amd64/amd64/lapic.c
===================================================================
RCS file: /cvs/src/sys/arch/amd64/amd64/lapic.c,v
retrieving revision 1.51
diff -u -p -r1.51 lapic.c
--- arch/amd64/amd64/lapic.c 20 Apr 2018 07:27:54 -0000 1.51
+++ arch/amd64/amd64/lapic.c 24 Jul 2018 21:55:40 -0000
@@ -174,13 +174,14 @@ lapic_cpu_number(void)
void
lapic_map(paddr_t lapic_base)
{
- int s;
pt_entry_t *pte;
vaddr_t va;
u_int64_t msr;
+ u_long s;
+ int tpr;
- disable_intr();
- s = lapic_tpr;
+ s = intr_disable();
+ tpr = lapic_tpr;
msr = rdmsr(MSR_APICBASE);
@@ -208,7 +209,7 @@ lapic_map(paddr_t lapic_base)
x2apic_enabled = 1;
codepatch_call(CPTAG_EOI, &x2apic_eoi);
- lapic_writereg(LAPIC_TPRI, s);
+ lapic_writereg(LAPIC_TPRI, tpr);
va = (vaddr_t)&local_apic;
} else {
/*
@@ -226,7 +227,7 @@ lapic_map(paddr_t lapic_base)
*pte = lapic_base | PG_RW | PG_V | PG_N | PG_G | pg_nx;
invlpg(va);
- lapic_tpr = s;
+ lapic_tpr = tpr;
}
/*
@@ -240,7 +241,7 @@ lapic_map(paddr_t lapic_base)
DPRINTF("%s: entered lapic page va 0x%llx pa 0x%llx\n", __func__,
(uint64_t)va, (uint64_t)lapic_base);
- enable_intr();
+ intr_restore(s);
}
/*
@@ -479,7 +480,7 @@ lapic_calibrate_timer(struct cpu_info *c
{
unsigned int startapic, endapic;
u_int64_t dtick, dapic, tmp;
- long rf = read_rflags();
+ u_long s;
int i;
if (mp_verbose)
@@ -493,7 +494,7 @@ lapic_calibrate_timer(struct cpu_info *c
lapic_writereg(LAPIC_DCR_TIMER, LAPIC_DCRT_DIV1);
lapic_writereg(LAPIC_ICR_TIMER, 0x80000000);
- disable_intr();
+ s = intr_disable();
/* wait for current cycle to finish */
wait_next_cycle();
@@ -505,7 +506,8 @@ lapic_calibrate_timer(struct cpu_info *c
wait_next_cycle();
endapic = lapic_gettick();
- write_rflags(rf);
+
+ intr_restore(s);
dtick = hz * rtclock_tval;
dapic = startapic-endapic;
Index: arch/amd64/amd64/machdep.c
===================================================================
RCS file: /cvs/src/sys/arch/amd64/amd64/machdep.c,v
retrieving revision 1.248
diff -u -p -r1.248 machdep.c
--- arch/amd64/amd64/machdep.c 12 Jul 2018 14:11:11 -0000 1.248
+++ arch/amd64/amd64/machdep.c 24 Jul 2018 21:55:40 -0000
@@ -1705,7 +1705,7 @@ init_x86_64(paddr_t first_avail)
softintr_init();
splraise(IPL_IPI);
- enable_intr();
+ intr_enable();
#ifdef DDB
db_machine_init();
@@ -1718,8 +1718,7 @@ init_x86_64(paddr_t first_avail)
void
cpu_reset(void)
{
-
- disable_intr();
+ intr_disable();
if (cpuresetfn)
(*cpuresetfn)();
Index: arch/amd64/amd64/tsc.c
===================================================================
RCS file: /cvs/src/sys/arch/amd64/amd64/tsc.c,v
retrieving revision 1.9
diff -u -p -r1.9 tsc.c
--- arch/amd64/amd64/tsc.c 8 Apr 2018 18:26:29 -0000 1.9
+++ arch/amd64/amd64/tsc.c 24 Jul 2018 21:55:40 -0000
@@ -120,7 +120,7 @@ uint64_t
measure_tsc_freq(struct timecounter *tc)
{
uint64_t count1, count2, frequency, min_freq, tsc1, tsc2;
- u_long ef;
+ u_long s;
int delay_usec, i, err1, err2, usec, success = 0;
/* warmup the timers */
@@ -133,14 +133,13 @@ measure_tsc_freq(struct timecounter *tc)
delay_usec = 100000;
for (i = 0; i < 3; i++) {
- ef = read_rflags();
- disable_intr();
+ s = intr_disable();
err1 = get_tsc_and_timecount(tc, &tsc1, &count1);
delay(delay_usec);
err2 = get_tsc_and_timecount(tc, &tsc2, &count2);
- write_rflags(ef);
+ intr_restore(s);
if (err1 || err2)
continue;
Index: arch/amd64/amd64/vmm.c
===================================================================
RCS file: /cvs/src/sys/arch/amd64/amd64/vmm.c,v
retrieving revision 1.216
diff -u -p -r1.216 vmm.c
--- arch/amd64/amd64/vmm.c 12 Jul 2018 10:16:41 -0000 1.216
+++ arch/amd64/amd64/vmm.c 24 Jul 2018 21:55:40 -0000
@@ -3905,6 +3905,7 @@ vcpu_run_vmx(struct vcpu *vcpu, struct v
struct vmx_invvpid_descriptor vid;
uint64_t eii, procbased, int_st;
uint16_t irq;
+ u_long s;
resume = 0;
irq = vrp->vrp_irq;
@@ -4099,9 +4100,9 @@ vcpu_run_vmx(struct vcpu *vcpu, struct v
#endif /* VMM_DEBUG */
/* Disable interrupts and save the current host FPU state. */
- disable_intr();
+ s = intr_disable();
if ((ret = vmm_fpurestore(vcpu))) {
- enable_intr();
+ intr_restore(s);
break;
}
@@ -4116,7 +4117,7 @@ vcpu_run_vmx(struct vcpu *vcpu, struct v
*/
vmm_fpusave(vcpu);
- enable_intr();
+ intr_restore(s);
exit_reason = VM_EXIT_NONE;
if (ret == 0) {
Index: arch/amd64/include/cpufunc.h
===================================================================
RCS file: /cvs/src/sys/arch/amd64/include/cpufunc.h,v
retrieving revision 1.29
diff -u -p -r1.29 cpufunc.h
--- arch/amd64/include/cpufunc.h 24 Jul 2018 14:49:44 -0000 1.29
+++ arch/amd64/include/cpufunc.h 24 Jul 2018 21:55:40 -0000
@@ -152,18 +152,6 @@ void setidt(int idx, /*XXX*/caddr_t func
/* XXXX ought to be in psl.h with spl() functions */
-static __inline void
-disable_intr(void)
-{
- __asm volatile("cli");
-}
-
-static __inline void
-enable_intr(void)
-{
- __asm volatile("sti");
-}
-
static __inline u_long
read_rflags(void)
{
@@ -182,7 +170,7 @@ write_rflags(u_long ef)
static __inline void
intr_enable(void)
{
- enable_intr();
+ __asm volatile("sti");
}
static __inline u_long
@@ -191,7 +179,7 @@ intr_disable(void)
u_long ef;
ef = read_rflags();
- disable_intr();
+ __asm volatile("cli");
return (ef);
}
Index: arch/amd64/isa/clock.c
===================================================================
RCS file: /cvs/src/sys/arch/amd64/isa/clock.c,v
retrieving revision 1.27
diff -u -p -r1.27 clock.c
--- arch/amd64/isa/clock.c 9 Jul 2018 19:38:33 -0000 1.27
+++ arch/amd64/isa/clock.c 24 Jul 2018 21:55:40 -0000
@@ -201,18 +201,17 @@ rtcintr(void *arg)
int
gettick(void)
{
- u_long ef;
+ u_long s;
u_char lo, hi;
/* Don't want someone screwing with the counter while we're here. */
mtx_enter(&timer_mutex);
- ef = read_rflags();
- disable_intr();
+ s = intr_disable();
/* Select counter 0 and latch it. */
outb(IO_TIMER1+TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
lo = inb(IO_TIMER1+TIMER_CNTR0);
hi = inb(IO_TIMER1+TIMER_CNTR0);
- write_rflags(ef);
+ intr_restore(s);
mtx_leave(&timer_mutex);
return ((hi << 8) | lo);
}
@@ -632,10 +631,9 @@ i8254_get_timecount(struct timecounter *
{
u_char hi, lo;
u_int count;
- u_long ef;
+ u_long s;
- ef = read_rflags();
- disable_intr();
+ s = intr_disable();
outb(IO_TIMER1+TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
lo = inb(IO_TIMER1+TIMER_CNTR0);
@@ -649,7 +647,8 @@ i8254_get_timecount(struct timecounter *
}
i8254_lastcount = count;
count += i8254_offset;
- write_rflags(ef);
+
+ intr_restore(s);
return (count);
}
Index: dev/pci/drm/drm_linux.h
===================================================================
RCS file: /cvs/src/sys/dev/pci/drm/drm_linux.h,v
retrieving revision 1.89
diff -u -p -r1.89 drm_linux.h
--- dev/pci/drm/drm_linux.h 25 Jun 2018 22:29:16 -0000 1.89
+++ dev/pci/drm/drm_linux.h 24 Jul 2018 21:55:41 -0000
@@ -898,8 +898,8 @@ void flush_delayed_work(struct delayed_w
typedef void *async_cookie_t;
#define async_schedule(func, data) (func)((data), NULL)
-#define local_irq_disable() disable_intr()
-#define local_irq_enable() enable_intr()
+#define local_irq_disable() intr_disable()
+#define local_irq_enable() intr_enable()
#define setup_timer(x, y, z) timeout_set((x), (void (*)(void *))(y), (void
*)(z))
#define mod_timer(x, y) timeout_add((x), (y - jiffies))
