On Wed, Jul 02, 2014 at 10:36:25PM -0700, Matthew Dempsky wrote:
> According to the "Intel 64 and IA-32 Architectures Software
> Developer's Manual", CPUID.80000001H:EDX.Page1GB [bit 26] indicates
> whether 1-GByte pages are supported with IA-32e paging.
>
> I think the diff below adds support for identifying this feature in
> dmesg, but my X201s is seemingly to old to support it.
Works for me with the last snapshot:
OpenBSD 5.5-current (GENERIC.MP) #272: Sun Jul 13 20:46:20 MDT 2014
[email protected]:/usr/src/sys/arch/amd64/compile/GENERIC.MP
real mem = 17042100224 (16252MB)
avail mem = 16579661824 (15811MB)
mpath0 at root
scsibus0 at mpath0: 256 targets
mainbus0 at root
bios0 at mainbus0: SMBIOS rev. 2.7 @ 0xec120 (82 entries)
bios0: vendor American Megatrends Inc. version "1.1a" date 01/03/2014
bios0: Supermicro X10SAE
acpi0 at bios0: rev 2
acpi0: sleep states S0 S1 S3 S4 S5
acpi0: tables DSDT FACP APIC FPDT LPIT SSDT SSDT SSDT SSDT MCFG HPET SSDT SSDT
ASF! DMAR EINJ ERST HEST BERT
acpi0: wakeup devices PS2K(S3) PS2M(S3) PXSX(S4) RP01(S4) PXSX(S4) RP02(S4)
PXSX(S4) RP03(S4) PXSX(S4) RP04(S4) PXSX(S4) RP05(S4) PXSX(S4) BR30(S4)
RP06(S4) PXSX(S4) [...]
acpitimer0 at acpi0: 3579545 Hz, 24 bits
acpimadt0 at acpi0 addr 0xfee00000: PC-AT compat
cpu0 at mainbus0: apid 0 (boot processor)
cpu0: Intel(R) Xeon(R) CPU E3-1246 v3 @ 3.50GHz, 3500.44 MHz
cpu0:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,SMX,EST,TM2,SSSE3,FMA3,CX16,xTPR,PDCM,PCID,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,AVX,F16C,RDRAND,NXE,PAGE1GB,LONG,LAHF,ABM,PERF,ITSC,FSGSBASE,BMI1,HLE,AVX2,SMEP,BMI2,ERMS,INVPCID,RTM
cpu0: 256KB 64b/line 8-way L2 cache
cpu0: smt 0, core 0, package 0
mtrr: Pentium Pro MTRR support, 10 var ranges, 88 fixed ranges
cpu0: apic clock running at 100MHz
cpu0: mwait min=64, max=64, C-substates=0.2.1.2.4, IBE
