On Mon, Jan 25, 2010 at 03:58:59PM +0100, Giovanni Bechis wrote:
> Giovanni Bechis wrote:
> >Stuart Henderson wrote:
> >>On 2010/01/25 00:50, Luis Henriques wrote:
> >>>Re-sending with "cvs diff -upRN"
> >
> Unfortunately this diff doesn't work with my card, I have "unable to
> reset hardware" errors whenever I try to scan the network or
> configure my device.
I took a look at the code again and one of the main things that is failing
is the correct identification of the chip. From my understanding of the
Linux code, the ah_radio should be identified as AR5K_AR2425.
So, I added a few lines to my initial patch so that this version of the chip
is correctly handled. Note, however, that I might have missed something:
as I told you before, I do not have this card so... no testing.
If you're able to test this patch, please let me know if anything changed
from previous patch.
Regards,
Luis
Index: dev/ic/ar5212.c
===================================================================
RCS file: /home/miguel/openbsd-cvsroot//src/sys/dev/ic/ar5212.c,v
retrieving revision 1.51
diff -u -p -r1.51 ar5212.c
--- dev/ic/ar5212.c 2 Jun 2009 12:39:02 -0000 1.51
+++ dev/ic/ar5212.c 26 Jan 2010 23:05:40 -0000
@@ -30,6 +30,7 @@ HAL_BOOL ar5k_ar5212_nic_wakeup(struct
u_int16_t ar5k_ar5212_radio_revision(struct ath_hal *, HAL_CHIP);
void ar5k_ar5212_fill(struct ath_hal *);
HAL_BOOL ar5k_ar5212_txpower(struct ath_hal *, HAL_CHANNEL *, u_int);
+void ar5k_ar5212_hw_set_sleep_clock(struct ath_hal *, HAL_BOOL);
/*
* Initial register setting for the AR5212
@@ -234,9 +235,17 @@ ar5k_ar5212_attach(u_int16_t device, voi
hal->ah_phy_spending = AR5K_AR5212_PHY_SPENDING_AR5424;
hal->ah_radio_5ghz_revision = hal->ah_radio_2ghz_revision =
AR5K_SREV_VER_AR5413;
- } else if (srev == AR5K_SREV_VER_AR2425) {
+ } else if (hal->ah_mac_version == (AR5K_SREV_VER_AR2425 >> 4) ||
+ hal->ah_mac_version == (AR5K_SREV_VER_AR2417 >> 4) ||
+ hal->ah_phy_revision == (AR5K_SREV_PHY_2425)) {
hal->ah_radio = AR5K_AR2425;
- hal->ah_phy_spending = AR5K_AR5212_PHY_SPENDING_AR5112;
+ hal->ah_single_chip = AH_TRUE;
+ hal->ah_radio_5ghz_revision= AR5K_SREV_RAD_2425;
+ } else if ((hal->ah_mac_version == (AR5K_SREV_VER_AR2424 >> 4)) ||
+ (hal->ah_phy_revision == AR5K_SREV_PHY_5413)) {
+ hal->ah_radio = AR5K_AR5413;
+ hal->ah_single_chip = AH_TRUE;
+ hal->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413;
} else if (hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112) {
hal->ah_radio = AR5K_AR5111;
hal->ah_phy_spending = AR5K_AR5212_PHY_SPENDING_AR5111;
@@ -262,6 +271,12 @@ ar5k_ar5212_attach(u_int16_t device, voi
}
hal->ah_phy = AR5K_AR5212_PHY(0);
+ /* Enable pci core retry fix on Hainan (5213A) and later chips */
+ if (srev >= AR5K_SREV_VER_AR5213A) {
+ AR5K_REG_ENABLE_BITS(AR5K_AR5212_PCICFG,
+ AR5K_AR5212_PCICFG_RETRY_FIX);
+ }
+
if (hal->ah_pci_express == AH_TRUE) {
/* PCI-Express based devices need some extra initialization */
ar5k_write_ini(hal, ar5212_pcie, nitems(ar5212_pcie), 0);
@@ -485,12 +500,13 @@ ar5k_ar5212_reset(struct ath_hal *hal, H
*/
if (chanchange == AH_TRUE) {
s_seq = AR5K_REG_READ(AR5K_AR5212_DCU_SEQNUM(0));
- s_ant = AR5K_REG_READ(AR5K_AR5212_DEFAULT_ANTENNA);
} else {
s_seq = 0;
- s_ant = 1;
}
+ /* Save default antenna */
+ s_ant = AR5K_REG_READ(AR5K_AR5212_DEFAULT_ANTENNA);
+
s_led[0] = AR5K_REG_READ(AR5K_AR5212_PCICFG) &
AR5K_AR5212_PCICFG_LEDSTATE;
s_led[1] = AR5K_REG_READ(AR5K_AR5212_GPIOCR);
@@ -544,6 +560,8 @@ ar5k_ar5212_reset(struct ath_hal *hal, H
return (AH_FALSE);
}
+ ar5k_ar5212_hw_set_sleep_clock(hal, AH_FALSE);
+
/* PHY access enable */
AR5K_REG_WRITE(AR5K_AR5212_PHY(0), AR5K_AR5212_PHY_SHIFT_5GHZ);
@@ -3034,3 +3052,75 @@ ar5k_ar5212_set_txpower_limit(struct ath
AR5K_PRINTF("changing txpower to %d\n", power);
return (ar5k_ar5212_txpower(hal, channel, power));
}
+
+/*
+ * If there is an external 32KHz crystal available, use it
+ * as ref. clock instead of 32/40MHz clock and baseband clocks
+ * to save power during sleep or restore normal 32/40MHz
+ * operation.
+ *
+ * XXX: When operating on 32KHz certain PHY registers (27 - 31,
+ * 123 - 127) require delay on access.
+ */
+void
+ar5k_ar5212_hw_set_sleep_clock(struct ath_hal *hal, HAL_BOOL enable)
+{
+ struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
+ u_int32_t scal, spending, usec32;
+
+ /* Only set 32KHz settings if we have an external
+ * 32KHz crystal present */
+ if ((AR5K_EEPROM_HAS32KHZCRYSTAL(ee->ee_misc1) ||
+ AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(ee->ee_misc1)) &&
+ enable) {
+ /* TODO */
+ } else {
+ /* Disable sleep clock operation and
+ * restore default parameters */
+ AR5K_REG_DISABLE_BITS(AR5K_AR5212_PCICFG,
+ AR5K_AR5212_PCICFG_SLEEP_CLOCK_EN);
+
+ AR5K_REG_WRITE_BITS(AR5K_AR5212_PCICFG,
+ AR5K_AR5212_PCICFG_SLEEP_CLOCK_RATE, 0);
+
+ AR5K_REG_WRITE(AR5K_AR5212_PHY_SCR, 0x1f);
+ AR5K_REG_WRITE(AR5K_AR5212_PHY_SLMT,
+ AR5K_AR5212_PHY_SLMT_32MHZ);
+
+ if (hal->ah_mac_version == (AR5K_SREV_VER_AR2417 >> 4))
+ scal = AR5K_AR5212_PHY_SCAL_32MHZ_2417;
+ else if (ee->ee_is_hb63 == AH_TRUE)
+ scal = AR5K_AR5212_PHY_SCAL_32MHZ_HB63;
+ else
+ scal = AR5K_AR5212_PHY_SCAL_32MHZ;
+
+ AR5K_REG_WRITE(AR5K_AR5212_PHY_SCAL, scal);
+
+ AR5K_REG_WRITE(AR5K_AR5212_PHY_SCLOCK,
+ AR5K_AR5212_PHY_SCLOCK_32MHZ);
+ AR5K_REG_WRITE(AR5K_AR5212_PHY_SDELAY,
+ AR5K_AR5212_PHY_SCLOCK_32MHZ);
+
+ if ((hal->ah_radio == AR5K_AR5112) ||
+ (hal->ah_radio == AR5K_AR5413) ||
+ (hal->ah_mac_version == (AR5K_SREV_VER_AR2417 >> 4)))
+ spending = 0x14;
+ else
+ spending = 0x18;
+
+ AR5K_REG_WRITE(AR5K_AR5212_PHY_SPENDING, spending);
+
+ if ((hal->ah_radio == AR5K_AR5112) ||
+ (hal->ah_radio == AR5K_AR5413))
+ usec32 = 39;
+ else
+ usec32 = 31;
+
+ AR5K_REG_WRITE_BITS(AR5K_AR5212_USEC,
+ AR5K_AR5212_USEC_32, usec32);
+
+ AR5K_REG_WRITE_BITS(AR5K_AR5212_TSF_PARM,
+ AR5K_AR5212_TSF_PARM_INC, 1);
+ }
+}
+
Index: dev/ic/ar5212reg.h
===================================================================
RCS file: /home/miguel/openbsd-cvsroot//src/sys/dev/ic/ar5212reg.h,v
retrieving revision 1.12
diff -u -p -r1.12 ar5212reg.h
--- dev/ic/ar5212reg.h 30 Jul 2008 07:15:39 -0000 1.12
+++ dev/ic/ar5212reg.h 26 Jan 2010 22:53:51 -0000
@@ -589,34 +589,38 @@ typedef enum {
/*
* PCI configuration register
*/
-#define AR5K_AR5212_PCICFG 0x4010
-#define AR5K_AR5212_PCICFG_CLKRUNEN 0x00000004
-#define AR5K_AR5212_PCICFG_EESIZE 0x00000018
-#define AR5K_AR5212_PCICFG_EESIZE_S 3
-#define AR5K_AR5212_PCICFG_EESIZE_4K 0
-#define AR5K_AR5212_PCICFG_EESIZE_8K 1
-#define AR5K_AR5212_PCICFG_EESIZE_16K 2
-#define AR5K_AR5212_PCICFG_EESIZE_FAIL 3
-#define AR5K_AR5212_PCICFG_LED 0x00000060
-#define AR5K_AR5212_PCICFG_LED_NONE 0x00000000
-#define AR5K_AR5212_PCICFG_LED_PEND 0x00000020
-#define AR5K_AR5212_PCICFG_LED_ASSOC 0x00000040
-#define AR5K_AR5212_PCICFG_BUS_SEL 0x00000380
-#define AR5K_AR5212_PCICFG_CBEFIX_DIS 0x00000400
-#define AR5K_AR5212_PCICFG_SL_INTEN 0x00000800
-#define AR5K_AR5212_PCICFG_SL_INPEN 0x00002800
-#define AR5K_AR5212_PCICFG_SPWR_DN 0x00010000
-#define AR5K_AR5212_PCICFG_LEDMODE 0x000e0000
-#define AR5K_AR5212_PCICFG_LEDMODE_PROP 0x00000000
-#define AR5K_AR5212_PCICFG_LEDMODE_PROM 0x00020000
-#define AR5K_AR5212_PCICFG_LEDMODE_PWR 0x00040000
-#define AR5K_AR5212_PCICFG_LEDMODE_RAND 0x00060000
-#define AR5K_AR5212_PCICFG_LEDBLINK 0x00700000
-#define AR5K_AR5212_PCICFG_LEDBLINK_S 20
-#define AR5K_AR5212_PCICFG_LEDSLOW 0x00800000
+#define AR5K_AR5212_PCICFG 0x4010
+#define AR5K_AR5212_PCICFG_SLEEP_CLOCK_EN 0x00000002 /* Enable sleep
clock */
+#define AR5K_AR5212_PCICFG_CLKRUNEN 0x00000004
+#define AR5K_AR5212_PCICFG_EESIZE 0x00000018
+#define AR5K_AR5212_PCICFG_EESIZE_S 3
+#define AR5K_AR5212_PCICFG_EESIZE_4K 0
+#define AR5K_AR5212_PCICFG_EESIZE_8K 1
+#define AR5K_AR5212_PCICFG_EESIZE_16K 2
+#define AR5K_AR5212_PCICFG_EESIZE_FAIL 3
+#define AR5K_AR5212_PCICFG_LED 0x00000060
+#define AR5K_AR5212_PCICFG_LED_NONE 0x00000000
+#define AR5K_AR5212_PCICFG_LED_PEND 0x00000020
+#define AR5K_AR5212_PCICFG_LED_ASSOC 0x00000040
+#define AR5K_AR5212_PCICFG_BUS_SEL 0x00000380
+#define AR5K_AR5212_PCICFG_CBEFIX_DIS 0x00000400
+#define AR5K_AR5212_PCICFG_SL_INTEN 0x00000800
+#define AR5K_AR5212_PCICFG_SL_INPEN 0x00002800
+#define AR5K_AR5212_PCICFG_RETRY_FIX 0x00001000 /* Enable pci core
retry fix */
+#define AR5K_AR5212_PCICFG_SPWR_DN 0x00010000
+#define AR5K_AR5212_PCICFG_LEDMODE 0x000e0000
+#define AR5K_AR5212_PCICFG_LEDMODE_PROP 0x00000000
+#define AR5K_AR5212_PCICFG_LEDMODE_PROM 0x00020000
+#define AR5K_AR5212_PCICFG_LEDMODE_PWR 0x00040000
+#define AR5K_AR5212_PCICFG_LEDMODE_RAND 0x00060000
+#define AR5K_AR5212_PCICFG_LEDBLINK 0x00700000
+#define AR5K_AR5212_PCICFG_LEDBLINK_S 20
+#define AR5K_AR5212_PCICFG_LEDSLOW 0x00800000
#define AR5K_AR5212_PCICFG_LEDSTATE \
(AR5K_AR5212_PCICFG_LED | AR5K_AR5212_PCICFG_LEDMODE | \
AR5K_AR5212_PCICFG_LEDBLINK | AR5K_AR5212_PCICFG_LEDSLOW)
+#define AR5K_AR5212_PCICFG_SLEEP_CLOCK_RATE 0x03000000 /* Sleep clock rate
*/
+#define AR5K_AR5212_PCICFG_SLEEP_CLOCK_RATE_S 24
/*
* "General Purpose Input/Output" (GPIO) control register
@@ -993,7 +997,7 @@ typedef enum {
* TSF parameter register
*/
#define AR5K_AR5212_TSF_PARM 0x8104
-#define AR5K_AR5212_TSF_PARM_INC_M 0x000000ff
+#define AR5K_AR5212_TSF_PARM_INC 0x000000ff
#define AR5K_AR5212_TSF_PARM_INC_S 0
/*
@@ -1099,6 +1103,8 @@ typedef enum {
#define AR5K_AR5212_PHY_SLMT_32MHZ 0x0000007f
#define AR5K_AR5212_PHY_SCAL 0x9878
#define AR5K_AR5212_PHY_SCAL_32MHZ 0x0000000e
+#define AR5K_AR5212_PHY_SCAL_32MHZ_2417 0x0000000a
+#define AR5K_AR5212_PHY_SCAL_32MHZ_HB63 0x00000032
/*
* PHY PLL control register
Index: dev/ic/ar5xxx.c
===================================================================
RCS file: /home/miguel/openbsd-cvsroot//src/sys/dev/ic/ar5xxx.c,v
retrieving revision 1.55
diff -u -p -r1.55 ar5xxx.c
--- dev/ic/ar5xxx.c 23 Sep 2009 18:03:30 -0000 1.55
+++ dev/ic/ar5xxx.c 26 Jan 2010 22:53:51 -0000
@@ -892,6 +892,12 @@ ar5k_eeprom_init(struct ath_hal *hal)
if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0);
AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1);
+
+ /* XXX: Don't know which versions include these two */
+ AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC2, ee_misc2);
+
+ if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3)
+ AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC3, ee_misc3);
}
if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_3) {
@@ -903,6 +909,12 @@ ar5k_eeprom_init(struct ath_hal *hal)
ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7;
ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7;
}
+
+ AR5K_EEPROM_READ(AR5K_EEPROM_IS_HB63, val);
+ if ((hal->ah_mac_version == (AR5K_SREV_VER_AR2425 >> 4)) && val)
+ ee->ee_is_hb63 = AH_TRUE;
+ else
+ ee->ee_is_hb63 = AH_FALSE;
/*
* Get conformance test limit values
Index: dev/ic/ar5xxx.h
===================================================================
RCS file: /home/miguel/openbsd-cvsroot//src/sys/dev/ic/ar5xxx.h,v
retrieving revision 1.47
diff -u -p -r1.47 ar5xxx.h
--- dev/ic/ar5xxx.h 24 Jul 2009 16:31:27 -0000 1.47
+++ dev/ic/ar5xxx.h 26 Jan 2010 22:53:51 -0000
@@ -645,6 +645,8 @@ struct ar5k_gain {
#define AR5K_EEPROM_INFO_CKSUM 0xffff
#define AR5K_EEPROM_INFO(_n) (AR5K_EEPROM_INFO_BASE + (_n))
+#define AR5K_EEPROM_IS_HB63 0x000b /* Talon detect */
+
#define AR5K_EEPROM_VERSION AR5K_EEPROM_INFO(1)
#define AR5K_EEPROM_VERSION_3_0 0x3000
#define AR5K_EEPROM_VERSION_3_1 0x3001
@@ -695,12 +697,15 @@ struct ar5k_gain {
#define AR5K_EEPROM_OBDB1_2GHZ 0x00ed
/* Misc values available since EEPROM 4.0 */
-#define AR5K_EEPROM_MISC0 0x00c4
-#define AR5K_EEPROM_EARSTART(_v) ((_v) & 0xfff)
-#define AR5K_EEPROM_EEMAP(_v) (((_v) >> 14) & 0x3)
-#define AR5K_EEPROM_MISC1 0x00c5
-#define AR5K_EEPROM_TARGET_PWRSTART(_v) ((_v) & 0xfff)
-#define AR5K_EEPROM_HAS32KHZCRYSTAL(_v) (((_v) >> 14) & 0x1)
+#define AR5K_EEPROM_MISC0 0x00c4
+#define AR5K_EEPROM_EARSTART(_v) ((_v) & 0xfff)
+#define AR5K_EEPROM_EEMAP(_v) (((_v) >> 14) & 0x3)
+#define AR5K_EEPROM_MISC1 0x00c5
+#define AR5K_EEPROM_TARGET_PWRSTART(_v) ((_v) & 0xfff)
+#define AR5K_EEPROM_HAS32KHZCRYSTAL(_v) (((_v) >> 14) & 0x1)
+#define AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(_v) (((_v) >> 15) & 0x1)
+#define AR5K_EEPROM_MISC2 0x00c6
+#define AR5K_EEPROM_MISC3 0x00c7
/* Some EEPROM defines */
#define AR5K_EEPROM_EEP_SCALE 100
@@ -749,8 +754,11 @@ struct ar5k_eeprom_info {
u_int16_t ee_version;
u_int16_t ee_header;
u_int16_t ee_ant_gain;
+ HAL_BOOL ee_is_hb63;
u_int16_t ee_misc0;
u_int16_t ee_misc1;
+ u_int16_t ee_misc2;
+ u_int16_t ee_misc3;
u_int16_t ee_cck_ofdm_gain_delta;
u_int16_t ee_cck_ofdm_power_delta;
u_int16_t ee_scaled_cck_delta;
@@ -1259,7 +1267,8 @@ struct ar5k_srev_name {
#define AR5K_SREV_VER_AR5414 0xa5
#define AR5K_SREV_VER_AR5416 0xc0 /* PCI-Express */
#define AR5K_SREV_VER_AR5418 0xca /* PCI-Express */
-#define AR5K_SREV_VER_AR2425 0xe2 /* PCI-Express */
+#define AR5K_SREV_VER_AR2425 0xe0 /* Swan */
+#define AR5K_SREV_VER_AR2417 0xf0 /* Nala */
#define AR5K_SREV_VER_UNSUPP 0xff
#define AR5K_SREV_RAD_5110 0x00
@@ -1271,10 +1280,15 @@ struct ar5k_srev_name {
#define AR5K_SREV_RAD_2112 0x40
#define AR5K_SREV_RAD_2112A 0x45
#define AR5K_SREV_RAD_SC0 0x56
+#define AR5K_SREV_RAD_5413 0x60
#define AR5K_SREV_RAD_SC1 0x63
#define AR5K_SREV_RAD_SC2 0xa2
+#define AR5K_SREV_RAD_2425 0xa2
#define AR5K_SREV_RAD_5133 0xc0
#define AR5K_SREV_RAD_UNSUPP 0xff
+
+#define AR5K_SREV_PHY_5413 0x61
+#define AR5K_SREV_PHY_2425 0x70
#define AR5K_DEVID_AR2413 0x001a
#define AR5K_DEVID_AR5413 0x001b
