Author: jkim
Date: Tue Nov 16 23:26:02 2010
New Revision: 215415
URL: http://svn.freebsd.org/changeset/base/215415
Log:
Restore CR0 after MTRR initialization for correctness sakes. There will be
no noticeable change because we enable caches before we enter here for both
BSP and AP cases. Remove another pointless optimization for CR4.PGE bit
while I am here.
Modified:
head/sys/amd64/amd64/amd64_mem.c
head/sys/i386/i386/i686_mem.c
Modified: head/sys/amd64/amd64/amd64_mem.c
==============================================================================
--- head/sys/amd64/amd64/amd64_mem.c Tue Nov 16 22:44:58 2010
(r215414)
+++ head/sys/amd64/amd64/amd64_mem.c Tue Nov 16 23:26:02 2010
(r215415)
@@ -307,17 +307,17 @@ amd64_mrstoreone(void *arg)
struct mem_range_desc *mrd;
u_int64_t omsrv, msrv;
int i, j, msr;
- u_int cr4save;
+ u_long cr0, cr4;
mrd = sc->mr_desc;
/* Disable PGE. */
- cr4save = rcr4();
- if (cr4save & CR4_PGE)
- load_cr4(cr4save & ~CR4_PGE);
+ cr4 = rcr4();
+ load_cr4(cr4 & ~CR4_PGE);
/* Disable caches (CD = 1, NW = 0). */
- load_cr0((rcr0() & ~CR0_NW) | CR0_CD);
+ cr0 = rcr0();
+ load_cr0((cr0 & ~CR0_NW) | CR0_CD);
/* Flushes caches and TLBs. */
wbinvd();
@@ -396,11 +396,9 @@ amd64_mrstoreone(void *arg)
/* Enable MTRRs. */
wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) | MTRR_DEF_ENABLE);
- /* Enable caches (CD = 0, NW = 0). */
- load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
-
- /* Restore PGE. */
- load_cr4(cr4save);
+ /* Restore caches and PGE. */
+ load_cr0(cr0);
+ load_cr4(cr4);
}
/*
Modified: head/sys/i386/i386/i686_mem.c
==============================================================================
--- head/sys/i386/i386/i686_mem.c Tue Nov 16 22:44:58 2010
(r215414)
+++ head/sys/i386/i386/i686_mem.c Tue Nov 16 23:26:02 2010
(r215415)
@@ -301,17 +301,17 @@ i686_mrstoreone(void *arg)
struct mem_range_desc *mrd;
u_int64_t omsrv, msrv;
int i, j, msr;
- u_int cr4save;
+ u_long cr0, cr4;
mrd = sc->mr_desc;
/* Disable PGE. */
- cr4save = rcr4();
- if (cr4save & CR4_PGE)
- load_cr4(cr4save & ~CR4_PGE);
+ cr4 = rcr4();
+ load_cr4(cr4 & ~CR4_PGE);
/* Disable caches (CD = 1, NW = 0). */
- load_cr0((rcr0() & ~CR0_NW) | CR0_CD);
+ cr0 = rcr0();
+ load_cr0((cr0 & ~CR0_NW) | CR0_CD);
/* Flushes caches and TLBs. */
wbinvd();
@@ -390,11 +390,9 @@ i686_mrstoreone(void *arg)
/* Enable MTRRs. */
wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) | MTRR_DEF_ENABLE);
- /* Enable caches (CD = 0, NW = 0). */
- load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
-
- /* Restore PGE. */
- load_cr4(cr4save);
+ /* Restore caches and PGE. */
+ load_cr0(cr0);
+ load_cr4(cr4);
}
/*
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