Author: jkim
Date: Tue Nov 16 22:44:58 2010
New Revision: 215414
URL: http://svn.freebsd.org/changeset/base/215414
Log:
Invalidate TLBs explicitly. r1.4 of sys/i386/i386/i686_mem.c removed this
code but probably it only worked by chance because modifying CR4.PGE bit
causes invlidation of entire TLBs. Since these are very rare events, this
micro-optimization seems useless.
Reviewed by: jhb
Modified:
head/sys/amd64/amd64/amd64_mem.c
head/sys/i386/i386/i686_mem.c
Modified: head/sys/amd64/amd64/amd64_mem.c
==============================================================================
--- head/sys/amd64/amd64/amd64_mem.c Tue Nov 16 22:23:20 2010
(r215413)
+++ head/sys/amd64/amd64/amd64_mem.c Tue Nov 16 22:44:58 2010
(r215414)
@@ -321,6 +321,7 @@ amd64_mrstoreone(void *arg)
/* Flushes caches and TLBs. */
wbinvd();
+ invltlb();
/* Disable MTRRs (E = 0). */
wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~MTRR_DEF_ENABLE);
@@ -388,8 +389,9 @@ amd64_mrstoreone(void *arg)
wrmsr(msr + 1, msrv);
}
- /* Flush caches, TLBs. */
+ /* Flush caches and TLBs. */
wbinvd();
+ invltlb();
/* Enable MTRRs. */
wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) | MTRR_DEF_ENABLE);
Modified: head/sys/i386/i386/i686_mem.c
==============================================================================
--- head/sys/i386/i386/i686_mem.c Tue Nov 16 22:23:20 2010
(r215413)
+++ head/sys/i386/i386/i686_mem.c Tue Nov 16 22:44:58 2010
(r215414)
@@ -315,6 +315,7 @@ i686_mrstoreone(void *arg)
/* Flushes caches and TLBs. */
wbinvd();
+ invltlb();
/* Disable MTRRs (E = 0). */
wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~MTRR_DEF_ENABLE);
@@ -382,8 +383,9 @@ i686_mrstoreone(void *arg)
wrmsr(msr + 1, msrv);
}
- /* Flush caches, TLBs. */
+ /* Flush caches and TLBs. */
wbinvd();
+ invltlb();
/* Enable MTRRs. */
wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) | MTRR_DEF_ENABLE);
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