Module Name: src
Committed By: msaitoh
Date: Mon Nov 13 15:08:06 UTC 2023
Modified Files:
src/sys/dev/ic: dwc_eqos_reg.h
Log Message:
eqos(4): Extend bitwidth of SYSBUS_MODE_{RD,WR}_OSR_LMT to 4bits.
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/dev/ic/dwc_eqos_reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/ic/dwc_eqos_reg.h
diff -u src/sys/dev/ic/dwc_eqos_reg.h:1.9 src/sys/dev/ic/dwc_eqos_reg.h:1.10
--- src/sys/dev/ic/dwc_eqos_reg.h:1.9 Mon Nov 13 15:07:19 2023
+++ src/sys/dev/ic/dwc_eqos_reg.h Mon Nov 13 15:08:06 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: dwc_eqos_reg.h,v 1.9 2023/11/13 15:07:19 msaitoh Exp $ */
+/* $NetBSD: dwc_eqos_reg.h,v 1.10 2023/11/13 15:08:06 msaitoh Exp $ */
/*-
* Copyright (c) 2022 Jared McNeill <jmcne...@invisible.ca>
@@ -229,9 +229,9 @@
#define GMAC_DMA_MODE_SWR (1U << 0)
#define GMAC_DMA_SYSBUS_MODE 0x1004
#define GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT 24
-#define GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK (0x3U << GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT)
+#define GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK (0xfU << GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT)
#define GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16
-#define GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK (0x7U << GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT)
+#define GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK (0xfU << GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT)
#define GMAC_DMA_SYSBUS_MODE_MB (1U << 14)
#define GMAC_DMA_SYSBUS_MODE_EAME (1U << 11)
#define GMAC_DMA_SYSBUS_MODE_BLEN16 (1U << 3)
