Module Name: src
Committed By: msaitoh
Date: Mon Nov 13 15:07:19 UTC 2023
Modified Files:
src/sys/dev/ic: dwc_eqos.c dwc_eqos_reg.h
Log Message:
eqos(4): Set bit 31 when writing MAC_ADDRESS0_HIGH register.
To generate a diff of this commit:
cvs rdiff -u -r1.33 -r1.34 src/sys/dev/ic/dwc_eqos.c
cvs rdiff -u -r1.8 -r1.9 src/sys/dev/ic/dwc_eqos_reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/ic/dwc_eqos.c
diff -u src/sys/dev/ic/dwc_eqos.c:1.33 src/sys/dev/ic/dwc_eqos.c:1.34
--- src/sys/dev/ic/dwc_eqos.c:1.33 Thu Nov 2 13:50:14 2023
+++ src/sys/dev/ic/dwc_eqos.c Mon Nov 13 15:07:19 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: dwc_eqos.c,v 1.33 2023/11/02 13:50:14 riastradh Exp $ */
+/* $NetBSD: dwc_eqos.c,v 1.34 2023/11/13 15:07:19 msaitoh Exp $ */
/*-
* Copyright (c) 2022 Jared McNeill <jmcne...@invisible.ca>
@@ -38,7 +38,7 @@
#include "opt_net_mpsafe.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: dwc_eqos.c,v 1.33 2023/11/02 13:50:14 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: dwc_eqos.c,v 1.34 2023/11/13 15:07:19 msaitoh Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -545,7 +545,7 @@ eqos_setup_rxfilter(struct eqos_softc *s
/* Write our unicast address */
eaddr = CLLADDR(ifp->if_sadl);
- val = eaddr[4] | (eaddr[5] << 8);
+ val = eaddr[4] | (eaddr[5] << 8) | GMAC_MAC_ADDRESS0_HIGH_AE;
WR4(sc, GMAC_MAC_ADDRESS0_HIGH, val);
val = eaddr[0] | (eaddr[1] << 8) | (eaddr[2] << 16) |
(eaddr[3] << 24);
Index: src/sys/dev/ic/dwc_eqos_reg.h
diff -u src/sys/dev/ic/dwc_eqos_reg.h:1.8 src/sys/dev/ic/dwc_eqos_reg.h:1.9
--- src/sys/dev/ic/dwc_eqos_reg.h:1.8 Thu Oct 26 18:02:50 2023
+++ src/sys/dev/ic/dwc_eqos_reg.h Mon Nov 13 15:07:19 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: dwc_eqos_reg.h,v 1.8 2023/10/26 18:02:50 msaitoh Exp $ */
+/* $NetBSD: dwc_eqos_reg.h,v 1.9 2023/11/13 15:07:19 msaitoh Exp $ */
/*-
* Copyright (c) 2022 Jared McNeill <jmcne...@invisible.ca>
@@ -120,6 +120,7 @@
#define GMAC_MAC_MDIO_DATA 0x0204
#define GMAC_MAC_CSR_SW_CTRL 0x0230
#define GMAC_MAC_ADDRESS0_HIGH 0x0300
+#define GMAC_MAC_ADDRESS0_HIGH_AE (1U << 31)
#define GMAC_MAC_ADDRESS0_LOW 0x0304
#define GMAC_MMC_CONTROL 0x0700
#define GMAC_MMC_CONTROL_UCDBC (1U << 8)
