Module Name: src
Committed By: jmcneill
Date: Sat Jun 25 12:41:56 UTC 2022
Modified Files:
src/sys/arch/aarch64/include: cpu.h
src/sys/arch/arm/broadcom: bcm2835_intr.c
src/sys/arch/arm/cortex: gic.c gicv3.c
src/sys/arch/arm/imx: imx23_icoll.c
src/sys/arch/arm/include: cpu.h
src/sys/arch/arm/marvell: armadaxp.c
src/sys/arch/arm/pic: pic.c
src/sys/arch/arm/sunxi: sunxi_intc.c
Log Message:
pic: Update ci_cpl in pic_set_priority callback.
Not all ICs need interrupts disabled to update the priority. DAIF accesses
are not cheap, so push the update of ci_cpl from pic_set_priority to the
IC's pic_set_priority callback, and let the IC driver determine whether
or not it needs interrupts disabled.
To generate a diff of this commit:
cvs rdiff -u -r1.45 -r1.46 src/sys/arch/aarch64/include/cpu.h
cvs rdiff -u -r1.42 -r1.43 src/sys/arch/arm/broadcom/bcm2835_intr.c
cvs rdiff -u -r1.53 -r1.54 src/sys/arch/arm/cortex/gic.c
cvs rdiff -u -r1.50 -r1.51 src/sys/arch/arm/cortex/gicv3.c
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/imx/imx23_icoll.c
cvs rdiff -u -r1.122 -r1.123 src/sys/arch/arm/include/cpu.h
cvs rdiff -u -r1.25 -r1.26 src/sys/arch/arm/marvell/armadaxp.c
cvs rdiff -u -r1.79 -r1.80 src/sys/arch/arm/pic/pic.c
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/sunxi/sunxi_intc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/include/cpu.h
diff -u src/sys/arch/aarch64/include/cpu.h:1.45 src/sys/arch/aarch64/include/cpu.h:1.46
--- src/sys/arch/aarch64/include/cpu.h:1.45 Tue Nov 2 11:26:03 2021
+++ src/sys/arch/aarch64/include/cpu.h Sat Jun 25 12:41:56 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.45 2021/11/02 11:26:03 ryo Exp $ */
+/* $NetBSD: cpu.h,v 1.46 2022/06/25 12:41:56 jmcneill Exp $ */
/*-
* Copyright (c) 2014, 2020 The NetBSD Foundation, Inc.
@@ -128,7 +128,7 @@ struct cpu_info {
int ci_mtx_count;
int ci_cpl; /* current processor level (spl) */
- int ci_hwpl; /* current hardware priority */
+ volatile int ci_hwpl; /* current hardware priority */
volatile u_int ci_softints;
volatile u_int ci_intr_depth;
volatile uint32_t ci_blocked_pics;
Index: src/sys/arch/arm/broadcom/bcm2835_intr.c
diff -u src/sys/arch/arm/broadcom/bcm2835_intr.c:1.42 src/sys/arch/arm/broadcom/bcm2835_intr.c:1.43
--- src/sys/arch/arm/broadcom/bcm2835_intr.c:1.42 Sun Oct 31 16:23:47 2021
+++ src/sys/arch/arm/broadcom/bcm2835_intr.c Sat Jun 25 12:41:55 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: bcm2835_intr.c,v 1.42 2021/10/31 16:23:47 skrll Exp $ */
+/* $NetBSD: bcm2835_intr.c,v 1.43 2022/06/25 12:41:55 jmcneill Exp $ */
/*-
* Copyright (c) 2012, 2015, 2019 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: bcm2835_intr.c,v 1.42 2021/10/31 16:23:47 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: bcm2835_intr.c,v 1.43 2022/06/25 12:41:55 jmcneill Exp $");
#define _INTR_PRIVATE
@@ -150,6 +150,7 @@ static int bcm2836mp_int_base[BCM2836_NC
static void
bcm2835_set_priority(struct pic_softc *pic, int ipl)
{
+ curcpu()->ci_cpl = ipl;
}
static struct pic_ops bcm2835_picops = {
Index: src/sys/arch/arm/cortex/gic.c
diff -u src/sys/arch/arm/cortex/gic.c:1.53 src/sys/arch/arm/cortex/gic.c:1.54
--- src/sys/arch/arm/cortex/gic.c:1.53 Thu Mar 3 06:26:28 2022
+++ src/sys/arch/arm/cortex/gic.c Sat Jun 25 12:41:55 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: gic.c,v 1.53 2022/03/03 06:26:28 riastradh Exp $ */
+/* $NetBSD: gic.c,v 1.54 2022/06/25 12:41:55 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -35,7 +35,7 @@
#define _INTR_PRIVATE
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.53 2022/03/03 06:26:28 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.54 2022/06/25 12:41:55 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -229,11 +229,14 @@ armgic_set_priority(struct pic_softc *pi
struct armgic_softc * const sc = PICTOSOFTC(pic);
struct cpu_info * const ci = curcpu();
- if (ipl < ci->ci_hwpl) {
+ while (ipl < ci->ci_hwpl) {
/* Lowering priority mask */
ci->ci_hwpl = ipl;
+ __insn_barrier();
gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(ipl));
}
+ __insn_barrier();
+ ci->ci_cpl = ipl;
}
#ifdef MULTIPROCESSOR
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.50 src/sys/arch/arm/cortex/gicv3.c:1.51
--- src/sys/arch/arm/cortex/gicv3.c:1.50 Mon Mar 28 19:59:35 2022
+++ src/sys/arch/arm/cortex/gicv3.c Sat Jun 25 12:41:55 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.50 2022/03/28 19:59:35 riastradh Exp $ */
+/* $NetBSD: gicv3.c,v 1.51 2022/06/25 12:41:55 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill <jmcne...@invisible.ca>
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.50 2022/03/28 19:59:35 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.51 2022/06/25 12:41:55 jmcneill Exp $");
#include <sys/param.h>
#include <sys/kernel.h>
@@ -237,11 +237,14 @@ gicv3_set_priority(struct pic_softc *pic
struct gicv3_softc * const sc = PICTOSOFTC(pic);
struct cpu_info * const ci = curcpu();
- if (ipl < ci->ci_hwpl) {
+ while (ipl < ci->ci_hwpl) {
/* Lowering priority mask */
ci->ci_hwpl = ipl;
+ __insn_barrier();
icc_pmr_write(IPL_TO_PMR(sc, ipl));
}
+ __insn_barrier();
+ ci->ci_cpl = ipl;
}
static void
Index: src/sys/arch/arm/imx/imx23_icoll.c
diff -u src/sys/arch/arm/imx/imx23_icoll.c:1.3 src/sys/arch/arm/imx/imx23_icoll.c:1.4
--- src/sys/arch/arm/imx/imx23_icoll.c:1.3 Tue Feb 25 08:39:39 2014
+++ src/sys/arch/arm/imx/imx23_icoll.c Sat Jun 25 12:41:56 2022
@@ -1,4 +1,4 @@
-/* $Id: imx23_icoll.c,v 1.3 2014/02/25 08:39:39 martin Exp $ */
+/* $Id: imx23_icoll.c,v 1.4 2022/06/25 12:41:56 jmcneill Exp $ */
/*
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -251,6 +251,8 @@ icoll_set_priority(struct pic_softc *pic
struct intrsource *is;
int i;
+ register_t psw = DISABLE_INTERRUPT_SAVE();
+
for (i = 0; i < pic->pic_maxsources; i++) {
is = pic->pic_sources[i];
if (is == NULL)
@@ -260,6 +262,12 @@ icoll_set_priority(struct pic_softc *pic
else
ICOLL_CLR_IRQ(sc, pic->pic_irqbase + is->is_irq);
}
+
+ curcpu()->ci_cpl = newipl;
+
+ if ((psw & I32_bit) == 0) {
+ ENABLE_INTERRUPT();
+ }
}
/*
Index: src/sys/arch/arm/include/cpu.h
diff -u src/sys/arch/arm/include/cpu.h:1.122 src/sys/arch/arm/include/cpu.h:1.123
--- src/sys/arch/arm/include/cpu.h:1.122 Sat Dec 18 16:41:37 2021
+++ src/sys/arch/arm/include/cpu.h Sat Jun 25 12:41:56 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.122 2021/12/18 16:41:37 riastradh Exp $ */
+/* $NetBSD: cpu.h,v 1.123 2022/06/25 12:41:56 jmcneill Exp $ */
/*
* Copyright (c) 1994-1996 Mark Brinicombe.
@@ -218,7 +218,7 @@ struct cpu_info {
ci_softc; /* platform softc */
int ci_cpl; /* current processor level (spl) */
- int ci_hwpl; /* current hardware priority */
+ volatile int ci_hwpl; /* current hardware priority */
int ci_kfpu_spl;
volatile u_int ci_intr_depth; /* */
Index: src/sys/arch/arm/marvell/armadaxp.c
diff -u src/sys/arch/arm/marvell/armadaxp.c:1.25 src/sys/arch/arm/marvell/armadaxp.c:1.26
--- src/sys/arch/arm/marvell/armadaxp.c:1.25 Tue May 31 11:22:33 2022
+++ src/sys/arch/arm/marvell/armadaxp.c Sat Jun 25 12:41:56 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: armadaxp.c,v 1.25 2022/05/31 11:22:33 andvar Exp $ */
+/* $NetBSD: armadaxp.c,v 1.26 2022/06/25 12:41:56 jmcneill Exp $ */
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
@@ -37,7 +37,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI
*******************************************************************************/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: armadaxp.c,v 1.25 2022/05/31 11:22:33 andvar Exp $");
+__KERNEL_RCSID(0, "$NetBSD: armadaxp.c,v 1.26 2022/06/25 12:41:56 jmcneill Exp $");
#define _INTR_PRIVATE
@@ -656,10 +656,18 @@ armadaxp_pic_set_priority(struct pic_sof
{
int ctp;
+ register_t psw = DISABLE_INTERRUPT_SAVE();
+
ctp = MPIC_CPU_READ(ARMADAXP_MLMB_MPIC_CTP);
ctp &= ~(0xf << MPIC_CTP_SHIFT);
ctp |= (ipl << MPIC_CTP_SHIFT);
MPIC_CPU_WRITE(ARMADAXP_MLMB_MPIC_CTP, ctp);
+
+ curcpu()->ci_cpl = ipl;
+
+ if ((psw & I32_bit) == 0) {
+ ENABLE_INTERRUPT();
+ }
}
static void
Index: src/sys/arch/arm/pic/pic.c
diff -u src/sys/arch/arm/pic/pic.c:1.79 src/sys/arch/arm/pic/pic.c:1.80
--- src/sys/arch/arm/pic/pic.c:1.79 Sun Jan 2 11:17:39 2022
+++ src/sys/arch/arm/pic/pic.c Sat Jun 25 12:41:56 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: pic.c,v 1.79 2022/01/02 11:17:39 riastradh Exp $ */
+/* $NetBSD: pic.c,v 1.80 2022/06/25 12:41:56 jmcneill Exp $ */
/*-
* Copyright (c) 2008 The NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
#include "opt_multiprocessor.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pic.c,v 1.79 2022/01/02 11:17:39 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pic.c,v 1.80 2022/06/25 12:41:56 jmcneill Exp $");
#include <sys/param.h>
#include <sys/atomic.h>
@@ -98,13 +98,12 @@ static int pic_init(void);
void
pic_set_priority(struct cpu_info *ci, int newipl)
{
- register_t psw = DISABLE_INTERRUPT_SAVE();
- if (pic_list[0] != NULL)
- (pic_list[0]->pic_ops->pic_set_priority)(pic_list[0], newipl);
- ci->ci_cpl = newipl;
- if ((psw & I32_bit) == 0) {
- ENABLE_INTERRUPT();
+ if (__predict_false(pic_list[0] == NULL)) {
+ ci->ci_cpl = newipl;
+ return;
}
+
+ pic_list[0]->pic_ops->pic_set_priority(pic_list[0], newipl);
}
#endif
Index: src/sys/arch/arm/sunxi/sunxi_intc.c
diff -u src/sys/arch/arm/sunxi/sunxi_intc.c:1.7 src/sys/arch/arm/sunxi/sunxi_intc.c:1.8
--- src/sys/arch/arm/sunxi/sunxi_intc.c:1.7 Wed Jan 27 03:10:20 2021
+++ src/sys/arch/arm/sunxi/sunxi_intc.c Sat Jun 25 12:41:56 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: sunxi_intc.c,v 1.7 2021/01/27 03:10:20 thorpej Exp $ */
+/* $NetBSD: sunxi_intc.c,v 1.8 2022/06/25 12:41:56 jmcneill Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcne...@invisible.ca>
@@ -29,7 +29,7 @@
#define _INTR_PRIVATE
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sunxi_intc.c,v 1.7 2021/01/27 03:10:20 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sunxi_intc.c,v 1.8 2022/06/25 12:41:56 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -121,6 +121,7 @@ sunxi_intc_establish_irq(struct pic_soft
static void
sunxi_intc_set_priority(struct pic_softc *pic, int ipl)
{
+ curcpu()->ci_cpl = ipl;
}
static const struct pic_ops sunxi_intc_picops = {
