On Thu, 21 Sep 2023 12:45:07 GMT, Fei Yang <[email protected]> wrote:
>> Hi, I have arranged tier1-3 test on linux-riscv64 platform. Thanks for
>> adding handling for riscv.
>
>> Hi, I have arranged tier1-3 test on linux-riscv64 platform. Thanks for
>> adding handling for riscv.
>
> Tier1-3 test is clean. The riscv part looks good except for the nit.
Thanks for the review { @RealFYang, @pchilano, @TheRealMDoerr }.
The "Updated after review" version contains the following changes.
1. The extra space in `interp_masm_riscv.cpp` was removed.
2. I'm now using `R0` as a scratch register in
`InterpreterMacroAssembler::save_interpreter_state` on PowerPC.
3. I removed some local variables in
`FreezeBase::relativize_interpreted_frame_metadata` and
`ThawBase::derelativize_interpreted_frame_metadata` that are no longer needed
(x86, AArch64 and RISC-V).
Runs tier1-4 ok on supported platforms. PowerPC and RISC-V was sanity tested
using Qemu.
Please check if still looks ok.
-------------
PR Comment: https://git.openjdk.org/jdk/pull/15815#issuecomment-1735406747
