> From: Paul Durrant
> Sent: Tuesday, August 4, 2020 9:42 PM
>
> From: Paul Durrant
>
> It's confusing and not consistent with the terminology introduced with
> 'dfn_t'.
> Just call them IOMMU page tables.
>
> Also remove a pointless check of the 'acpi_drhd_units' list in
> vtd_dump_page_tabl
> From: Paul Durrant
> Sent: Tuesday, August 4, 2020 9:42 PM
>
> From: Paul Durrant
>
> This makes the code a little easier to read and also makes it more consistent
> with iremap_entry.
I feel the original readability is slightly better, as ctp is less obvious than
set_root_value, get_context
> From: Paul Durrant
> Sent: Tuesday, August 4, 2020 9:42 PM
>
> From: Paul Durrant
>
> This removes the need for much shifting, masking and several magic
> numbers.
> On the whole it makes the code quite a bit more readable.
similarly, I feel the readability is worse such as slptp. We may use
> From: Jan Beulich
> Sent: Wednesday, May 20, 2020 7:11 PM
>
> On 11.05.2020 19:43, buy computer wrote:
> > I've been working on a Windows 10 HVM on a Debian 10 dom0. When I
> was first
> > trying to make the VM, I was getting IOMMU errors. I had a hard time
> > figuring out what to do about thi
> From: Juergen Gross
> Sent: Tuesday, May 19, 2020 3:21 PM
>
> In case opt_ept_ad has not been set explicitly by the user via command
> line or runtime parameter, it is treated as "no" on Avoton cpus.
>
> Change that handling by setting opt_ept_ad to 0 for this cpu type
> explicitly if no user
> From: Lengyel, Tamas
> Sent: Saturday, May 23, 2020 12:34 AM
>
> When running shallow forks without device models it may be undesirable for
> Xen
what is shallow forks? and why interrupt injection is not desired without
device model? If it means just without Qemu thing, you still get local API
You may search dma_map* in drivers/gpu/drm/i915, and then print mapped
addresses to see any match in VT-d reported faulting addresses. For example,
__setup_page_dma might be one example that you want to check.
From: buy computer
Sent: Monday, May 25, 2020 1:18 PM
To: Tian, Kevin ; xen-devel
> From: Jan Beulich
> Sent: Monday, May 25, 2020 11:04 PM
>
> For lbr_tsx_fixup_check() simply name a few more specific erratum
> numbers.
>
> For bdf93_fixup_check(), however, more models are affected. Oddly enough
> despite being the same model and stepping, the erratum is listed for
> Xeon E3
> From: Lengyel, Tamas
> Sent: Monday, June 1, 2020 9:22 PM
>
> When running VM forks without device models (QEMU), it may
> be undesirable for Xen to inject interrupts. When creating such forks from
> Windows VMs we have observed the kernel trying to process interrupts
> immediately after the fo
> From: Tian, Kevin
> Sent: Wednesday, June 10, 2020 7:44 AM
>
> > From: Lengyel, Tamas
> > Sent: Monday, June 1, 2020 9:22 PM
> >
> > When running VM forks without device models (QEMU), it may
> > be undesirable for Xen to inject interrupts. When creating
Xen-devel ; Jan Beulich
> ; Wei Liu ; Roger Pau Monné
> ; Nakajima, Jun ; Tian,
> Kevin ; George Dunlap ;
> Ian Jackson ; Julien Grall ;
> Stefano Stabellini
> Subject: Re: [PATCH v1 0/7] Implement support for external IPT monitoring
>
> - 16 cze 2020 o 20:17, Andrew Coope
> From: Lengyel, Tamas
> Sent: Thursday, June 18, 2020 10:39 PM
>
> While forking VMs running a small RTOS system (Zephyr) a Xen crash has
> been
> observed due to a mm-lock order violation while copying the HVM CPU
> context
> from the parent. This issue has been identified to be due to
> hap_up
> From: Jan Beulich
> Sent: Thursday, June 18, 2020 2:38 PM
>
> * Guests outside of long mode can't have PCID enabled. Drop the
> respective check to make more obvious that there's no security issue
> (from potentially accessing past the mapped page's boundary).
>
> * Only the low 32 bits of
> From: Andrew Cooper [mailto:andrew.coop...@citrix.com]
> Sent: Thursday, June 27, 2019 3:02 AM
>
> From: Sergey Dyasli
>
> Otherwise hvm_set_cr0() will check the wrong CR4 bits (L1 instead of L2
> and vice-versa).
>
> Signed-off-by: Sergey Dyasli
> Reviewed-by: Andrew Cooper
Acked-by: Kevi
> From: Roger Pau Monne [mailto:roger@citrix.com]
> Sent: Friday, June 7, 2019 5:22 PM
>
> And fix it's only caller.
>
> Signed-off-by: Roger Pau Monné
> Reviewed-by: Paul Durrant
Reviewed-by: Kevin Tian
___
Xen-devel mailing list
Xen-devel@list
> From: Roger Pau Monne [mailto:roger@citrix.com]
> Sent: Friday, June 7, 2019 5:22 PM
>
> And fix it's only caller.
>
> Signed-off-by: Roger Pau Monné
Reviewed-by: Kevin Tian
___
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://list
> From: Roger Pau Monne [mailto:roger@citrix.com]
> Sent: Friday, June 7, 2019 5:22 PM
>
> This reduces the number of parameters of the function to two, and
> simplifies some of the calling sites.
>
> Signed-off-by: Roger Pau Monné
Reviewed-by: Kevin Tian
__
> From: Roger Pau Monne [mailto:roger@citrix.com]
> Sent: Friday, June 7, 2019 5:22 PM
>
> This reduces the number of parameters of the function to two, and
> simplifies some of the calling sites.
>
> Signed-off-by: Roger Pau Monné
Reviewed-by: Kevin Tian
__
> From: Roger Pau Monne [mailto:roger@citrix.com]
> Sent: Friday, June 7, 2019 5:22 PM
>
> This reduces the number of parameters of the function to two, and
> simplifies some of the calling sites.
>
> Signed-off-by: Roger Pau Monné
Reviewed-by: Kevin Tian
> From: Roger Pau Monne [mailto:roger@citrix.com]
> Sent: Wednesday, July 3, 2019 7:33 PM
>
> EPT differs from NPT and shadow when translating page orders to levels
> in the physmap page tables. EPT page tables level for order 0 pages is
> 0, while NPT and shadow instead use 1, ie: EPT page ta
> From: Andrew Cooper [mailto:andrew.coop...@citrix.com]
> Sent: Wednesday, July 17, 2019 12:24 AM
>
> DMA-ing to the stack is considered bad practice. In this case, if a
> timeout occurs because of a sluggish device which is processing the
> request, the completion notification will corrupt the
> From: Paul Durrant [mailto:paul.durr...@citrix.com]
> Sent: Tuesday, July 16, 2019 6:17 PM
>
> It's not vendor specific so it doesn't really belong there.
>
> Scanning the PCI topology also really doesn't have much to do with IOMMU
> initialization. It doesn't depend on there even being an IOMM
> From: Jan Beulich [mailto:jbeul...@suse.com]
> Sent: Tuesday, July 16, 2019 3:41 PM
>
> In line with "x86/IRQ: desc->affinity should strictly represent the
> requested value" the internally used IRQ(s) also shouldn't be restricted
> to online ones. Make set_desc_affinity() (set_msi_affinity() th
> From: Jan Beulich
> Sent: Friday, March 11, 2022 12:22 AM
>
> On 15.02.2022 14:27, Jan Beulich wrote:
> > On 15.02.2022 12:28, Roger Pau Monne wrote:
> >> After the removal of PVHv1 it's no longer supported to create a domain
> >> using hardware virtualization extensions and without a local API
> From: Jan Beulich
> Sent: Friday, February 18, 2022 4:31 PM
>
> On 18.02.2022 06:20, Tian, Kevin wrote:
> >> From: Jan Beulich
> >> Sent: Tuesday, January 11, 2022 12:36 AM
> >>
> >> When a page table ends up with no present entries left, it ca
> From: Roger Pau Monne
> Sent: Friday, February 25, 2022 12:37 AM
>
> Introduce a new field to mark devices as broken: having it set
> prevents the device from being assigned to guests. Use the field in
> order to mark ATS devices that have failed a flush as broken, thus
> preventing them to be
> From: Jan Beulich
> Sent: Monday, March 7, 2022 8:40 PM
>
> As of 3e56754b0887 ("xen/cet: Fix __initconst_cf_clobber") there's no
> need for a non-void return value anymore, as the hook functions are no
> longer themselves passed to __initcall(). For the same reason the
> iommu_enabled checks c
> From: Jan Beulich
> Sent: Tuesday, March 8, 2022 11:27 PM
>
> For an unknown reason I added back the operator while backporting,
> despite 4.16 having c06e3d810314 ("VT-d: per-domain IOMMU bitmap needs
> to have dynamic size"). I can only assume that I mistakenly took the
> 4.15 backport as bas
> From: Jan Beulich
> Sent: Monday, February 28, 2022 3:36 PM
>
> On 25.02.2022 18:11, Andrew Cooper wrote:
> > On 25/02/2022 13:19, Jan Beulich wrote:
> >> On 25.02.2022 13:28, Andrew Cooper wrote:
> >>> On 25/02/2022 08:44, Jan Beulich wrote:
> On 24.02.2022 20:48, Andrew Cooper wrote:
> >
> From: Jane Malalane
> Sent: Monday, March 7, 2022 11:06 PM
>
> Add XEN_SYSCTL_PHYSCAP_ARCH_ASSISTED_xapic and
> XEN_SYSCTL_PHYSCAP_ARCH_ASSISTED_x2apic to report accelerated xapic
> and x2apic, on x86 hardware.
> No such features are currently implemented on AMD hardware.
>
> HW assisted xAPIC
> From: Lengyel, Tamas
> Sent: Friday, March 11, 2022 2:45 AM
>
> During VM fork resetting a failed vmentry has been observed when the reset
> is performed immediately after a STI instruction executed. This is due to
> the guest interruptibility state in the VMCS being modified by STI but the
> s
> From: Jan Beulich
> Sent: Monday, March 14, 2022 3:33 PM
>
> On 14.03.2022 05:01, Tian, Kevin wrote:
> >> From: Jan Beulich
> >> Sent: Friday, February 18, 2022 4:31 PM
> >>
> >> On 18.02.2022 06:20, Tian, Kevin wrote:
> >>>> Fro
> From: Jan Beulich
> Sent: Monday, March 14, 2022 3:43 PM
>
> On 14.03.2022 07:35, Tian, Kevin wrote:
> >> From: Jan Beulich
> >> Sent: Monday, February 28, 2022 3:36 PM
> >>
> >> On 25.02.2022 18:11, Andrew Cooper wrote:
> >>> On 25/
> From: Tamas K Lengyel
> Sent: Monday, March 14, 2022 8:14 PM
>
> On Mon, Mar 14, 2022 at 3:22 AM Tian, Kevin wrote:
> >
> > > From: Lengyel, Tamas
> > > Sent: Friday, March 11, 2022 2:45 AM
> > >
> > > During VM fork resetting a fail
> From: Jane Malalane
> Sent: Wednesday, March 16, 2022 5:13 PM
>
> Add XEN_SYSCTL_PHYSCAP_X86_ASSISTED_XAPIC and
> XEN_SYSCTL_PHYSCAP_X86_ASSISTED_X2APIC to report accelerated xAPIC
> and
> x2APIC, on x86 hardware. This is so that xAPIC and x2APIC virtualization
> can subsequently be enabled on a
> From: Lengyel, Tamas
> Sent: Friday, March 25, 2022 9:33 PM
>
> During VM forking and resetting a failed vmentry has been observed due
> to the guest non-register state going out-of-sync with the guest register
> state. For example, a VM fork reset right after a STI instruction can trigger
> th
> From: Jan Beulich
> Sent: Thursday, April 7, 2022 3:50 PM
>
> On 07.04.2022 09:41, Roger Pau Monné wrote:
> > On Thu, Apr 07, 2022 at 08:11:06AM +0200, Jan Beulich wrote:
> >> First there's a printk() which actually wrongly uses pdev in the first
> >> place: We want to log the coordinates of th
> From: Jan Beulich
> Sent: Thursday, April 7, 2022 2:12 PM
>
> Despite the comment there infinite recursion was still possible, by
> flip-flopping between two domains. This is because prev_dom is derived
> from the DID found in the context entry, which was already updated by
> the time error rec
> From: Jan Beulich
> Sent: Thursday, April 7, 2022 5:28 PM
>
> If get_iommu_domid() in domain_context_unmap_one() fails, we better
> wouldn't clear the context entry in the first place, as we're then unable
> to issue the corresponding flush. However, we have no need to look up the
> DID in the
> From: Jane Malalane
> Sent: Friday, April 1, 2022 6:47 PM
>
> Add XEN_SYSCTL_PHYSCAP_X86_ASSISTED_XAPIC and
> XEN_SYSCTL_PHYSCAP_X86_ASSISTED_X2APIC to report accelerated xAPIC
> and
> x2APIC, on x86 hardware. This is so that xAPIC and x2APIC virtualization
> can subsequently be enabled on a pe
> From: Jan Beulich
> Sent: Monday, April 11, 2022 5:36 PM
>
> Prior extension of these functions to enable per-device quarantine page
> tables already didn't add more locking there, but merely left in place
> what had been there before. But really locking is unnecessary here:
> We're running wit
> From: Jan Beulich
> Sent: Monday, April 11, 2022 5:36 PM
>
> It's not only misplaced, but entirely unused.
>
> Signed-off-by: Jan Beulich
Reviewed-by: Kevin Tian
>
> --- a/xen/drivers/passthrough/vtd/iommu.h
> +++ b/xen/drivers/passthrough/vtd/iommu.h
> @@ -204,7 +204,6 @@ struct context_
> From: Jan Beulich
> Sent: Monday, April 11, 2022 5:37 PM
>
> While 97af062b89d5 ("IOMMU/x86: maintain a per-device pseudo domain
> ID")
> took care of not making things worse, plugging pre-existing leaks wasn't
> the purpose of that change; they're not security relevant after all.
>
> Signed-o
> From: Jan Beulich
> Sent: Monday, April 11, 2022 5:37 PM
>
> The field taking the value 7 (resulting in 18-bit DIDs when using the
> calculation in cap_ndoms(), when the DID fields are only 16 bits wide)
> is reserved. Instead of misbehaving in case we would encounter such an
> IOMMU, refuse to
> From: Jan Beulich
> Sent: Monday, April 11, 2022 5:40 PM
>
> There's no good reason to use these when we already have a pci_sbdf_t
> type object available. This extends to the use of PCI_BUS() in
> pci_ecam_map_bus() as well.
>
> No change to generated code (with gcc11 at least, and I have to
> From: Jan Beulich
> Sent: Monday, April 11, 2022 5:42 PM
>
> At their use sites the numeric suffixes are at least odd to read, first
> and foremost for PCI_DEVFN2() where the suffix doesn't even match the
> number of arguments. Make use of count_args() such that a single flavor
> each suffices
> From: Tamas K Lengyel
> Sent: Tuesday, April 19, 2022 2:43 AM
>
> On Fri, Mar 25, 2022 at 9:34 AM Tamas K Lengyel
> wrote:
> >
> > During VM forking and resetting a failed vmentry has been observed due
> > to the guest non-register state going out-of-sync with the guest register
> > state. For
> From: Jan Beulich
> Sent: Monday, October 11, 2021 4:49 PM
>
> Linux'es supposedly equivalent "intel_iommu=igfx_off" deals with any
> graphics devices (not just Intel ones) while at the same time limiting
> the effect to IOMMUs covering only graphics devices. Keying the decision
> to leave tran
> From: Jan Beulich
> Sent: Monday, October 11, 2021 4:50 PM
>
> BIOSes, when enabling the dedicated DMAR unit for the sound device,
> need to also set a non-zero number of TLB entries in a respective
> system management register (VTISOCHCTRL). At least one BIOS is known
> to fail to do so, causi
> From: Jan Beulich
> Sent: Tuesday, October 19, 2021 8:52 PM
>
> With NPT or shadow in use, the p2m_set_entry() -> p2m_pt_set_entry() ->
> write_p2m_entry() -> p2m_flush_nestedp2m() call sequence triggers a lock
> order violation when the PoD lock is held around it. Hence such flushing
> needs t
> From: Jan Beulich
> Sent: Friday, October 22, 2021 1:59 PM
>
> On 21.10.2021 11:58, Jan Beulich wrote:
> > x2apic_bsp_setup() gets called ahead of iommu_setup(), and since x2APIC
> > mode (physical vs clustered) depends on iommu_intremap, that variable
> > needs to be set to off as soon as we k
> From: Jan Beulich
> Sent: Tuesday, November 9, 2021 10:56 PM
>
> 1: per-domain IOMMU bitmap needs to have dynamic size
> 2: fix reduced page table levels support when sharing tables
> 3: don't needlessly engage the untrusted-MSI workaround
>
> As to 4.16 considerations: Only patch 1 addresses
> From: Jan Beulich
> Sent: Friday, November 12, 2021 5:51 PM
>
> cap_super_page_val() and cap_super_offset() are unused (apart from the
> latter using the former). I don't see how cap_super_offset() can be
> useful in its current shape: cap_super_page_val()'s result is not an
> lvalue and hence
> From: Roger Pau Monné
> Sent: Friday, November 12, 2021 8:19 PM
>
> On Fri, Nov 12, 2021 at 01:07:33PM +0100, Jan Beulich wrote:
> > On 12.11.2021 12:23, Roger Pau Monné wrote:
> > > On Fri, Nov 12, 2021 at 10:47:59AM +0100, Jan Beulich wrote:
> > >> Merely setting bit 0 in the bitmap is insuff
> From: Jan Beulich
> Sent: Friday, November 12, 2021 5:48 PM
>
> Merely setting bit 0 in the bitmap is insufficient, as then Dom0 will
> still have DID 0 allocated to it, because of the zero-filling of
> domid_map[]. Set slot 0 to DOMID_INVALID to keep DID 0 from getting
> used.
>
> Fixes: b9c2
> From: Jan Beulich
> Sent: Friday, November 12, 2021 5:48 PM
>
> This logic will want invoking from elsewhere.
>
> Signed-off-by: Jan Beulich
Reviewed-by: Kevin Tian
>
> --- a/xen/drivers/passthrough/vtd/iommu.c
> +++ b/xen/drivers/passthrough/vtd/iommu.c
> @@ -157,6 +157,51 @@ static void
> From: Jan Beulich
> Sent: Friday, November 12, 2021 5:49 PM
>
> While domain_context_mapping() invokes domain_context_unmap() in a
> sub-
> case of handling DEV_TYPE_PCI when encountering an error, thus avoiding
> a leak, individual calls to domain_context_mapping_one() aren't
> similarly cover
> From: Jan Beulich
> Sent: Friday, November 12, 2021 5:49 PM
>
> - Correct struct field type.
> - Use unsigned int when that suffices.
> - Eliminate a (badly typed) local variable from
> context_set_domain_id().
> - Don't use -EFAULT inappropriately.
> - Move set_bit() such that it won't be do
> From: Jan Beulich
> Sent: Friday, November 12, 2021 5:50 PM
>
> This is in preparation of adding another "translation" method. Take the
> combination of the extra validation both previously open-coded have been
> doing: Bounds check and bitmap check. But don't propagate the previous
> pointless
> From: Jan Beulich
> Sent: Friday, November 12, 2021 5:50 PM
>
> When an IOMMU implements the full 16 bits worth of DID in context
> entries, there's no point going through a memory base translation table.
> For IOMMUs not using Caching Mode we can simply use the domain IDs
> verbatim, while for
> From: Jan Beulich
> Sent: Tuesday, November 23, 2021 9:40 PM
>
> Bit 0 of the capability register field has become reserved at or before
Bit 0 of 'SAGAW' in the capability register ...
> spec version 2.2. Treat it as such. Replace the effective open-coding of
> find_first_set_bit(). Adjust lo
> From: Jan Beulich
> Sent: Tuesday, November 23, 2021 9:40 PM
>
> All our present implementation requires is that the range fully fits
> in a single page. No need to exclude the case of the last register
> extending right to the end of that page.
>
> Signed-off-by: Jan Beulich
Reviewed-by: Ke
> From: Jan Beulich
> Sent: Tuesday, November 23, 2021 9:40 PM
>
> As of commit 6773b1a7584a ("VT-d: Don't assume register-based
> invalidation is always supported") we don't (try to) use register based
> invalidation anymore when that's not supported by hardware. Hence
> there's also no point in
> From: Beulich
> Sent: Wednesday, January 5, 2022 9:58 PM
>
> This has gone out of sync over time. Introduce a simplistic mechanism to
> hopefully keep things in sync going forward.
>
> Also limit the array index to just the "basic exit reason" part, which is
> what the pseudo-enumeration covers
> From: Jan Beulich
> Sent: Tuesday, January 11, 2022 12:23 AM
>
> In order to be able to insert/remove super-pages we need to allow
> callers of the walking function to specify at which point to stop the
> walk.
>
> For intel_iommu_lookup_page() integrate the last level access into
> the main w
> From: Jan Beulich
> Sent: Tuesday, January 11, 2022 12:23 AM
>
> I have to admit that I never understood why domain_pgd_maddr() wants to
> populate all page table levels for DFN 0. I can only assume that despite
> the comment there what is needed is population just down to the smallest
> possib
> From: Jan Beulich
> Sent: Tuesday, January 11, 2022 12:32 AM
>
> ... depending on feature availability (and absence of quirks).
>
> Also make the page table dumping function aware of superpages.
>
> Signed-off-by: Jan Beulich
Reviewed-by: Kevin Tian
> ---
> v3: Rename queue_free_pt()'s las
> From: Jan Beulich
> Sent: Tuesday, January 11, 2022 12:34 AM
>
> Having a separate flush-all hook has always been puzzling me some. We
> will want to be able to force a full flush via accumulated flush flags
> from the map/unmap functions. Introduce a respective new flag and fold
> all flush ha
> From: Jan Beulich
> Sent: Tuesday, January 11, 2022 12:35 AM
>
> Page tables are used for two purposes after allocation: They either
> start out all empty, or they get filled to replace a superpage.
> Subsequently, to replace all empty or fully contiguous page tables,
> contiguous sub-regions w
> From: Jan Beulich
> Sent: Tuesday, January 11, 2022 12:36 AM
>
> When a page table ends up with no present entries left, it can be
> replaced by a non-present entry at the next higher level. The page table
> itself can then be scheduled for freeing.
>
> Note that while its output isn't used th
> From: Jan Beulich
> Sent: Tuesday, January 11, 2022 12:38 AM
>
> When a page table ends up with all contiguous entries (including all
> identical attributes), it can be replaced by a superpage entry at the
> next higher level. The page table itself can then be scheduled for
> freeing.
>
> The
> From: Jan Beulich
> Sent: Tuesday, January 11, 2022 12:39 AM
>
> Signed-off-by: Jan Beulich
Reviewed-by: Kevin tian
> ---
> v3: New.
>
> --- a/xen/drivers/passthrough/amd/iommu_map.c
> +++ b/xen/drivers/passthrough/amd/iommu_map.c
> @@ -283,6 +283,8 @@ static int iommu_pde_from_dfn(struct
> From: Andrew Cooper
> Sent: Friday, January 21, 2022 7:23 PM
>
> This is a trivial accessor for an MSR, so use hvm_get_reg() rather than a
> dedicated hook. In arch_get_info_guest(), rework the logic to read
> GS_SHADOW
> only once.
>
> get_hvm_registers() is called on current, meaning that d
> From: Jan Beulich
> Sent: Thursday, January 27, 2022 10:48 PM
>
> The actual function should always have lived in core x86 code; move it
> there, replacing get_cache_line_size() by readily available (except very
> early during boot; see the code comment) data. Also rename the function.
>
> Dro
> From: Jan Beulich
> Sent: Thursday, January 27, 2022 10:49 PM
>
> Let's use infrastructure we have available instead of an open-coded
> wbinvd() invocation.
>
> Signed-off-by: Jan Beulich
Reviewed-by: Kevin Tian
>
> --- a/xen/drivers/passthrough/vtd/extern.h
> +++ b/xen/drivers/passthrough
> From: Jan Beulich
> Sent: Thursday, January 27, 2022 10:50 PM
>
> The VT-d hook can indicate an error, which shouldn't be ignored. Convert
> the hook's return value to a proper error code, and let that bubble up.
>
> Signed-off-by: Jan Beulich
> ---
> I'm not convinced of the XSM related beha
> From: Jan Beulich
> Sent: Friday, February 18, 2022 4:25 PM
>
> On 18.02.2022 06:01, Tian, Kevin wrote:
> >> From: Jan Beulich
> >> Sent: Tuesday, January 11, 2022 12:35 AM
> >>
> >> Page tables are used for two purposes after allocation: T
> From: Andrew Cooper
> Sent: Thursday, January 19, 2023 3:37 AM
>
> The original patch tried to do two things - implement VMNotify, and
> re-optimise VT-x to not intercept #DB/#AC by default.
>
> The second part is buggy in multiple ways. Both GDBSX and Introspection
> need
> to conditionally
> From: Jan Beulich
> Sent: Friday, January 20, 2023 4:44 PM
>
> First of all the variable is meaningful only when an IOMMU is in use for
> a guest. Qualify the check accordingly, like done elsewhere. Furthermore
> the controlling command line option is supposed to take effect on VT-d
> only. Sin
> From: Xenia Ragiadakou
> Sent: Tuesday, January 24, 2023 8:42 PM
>
> The variable untrusted_msi indicates whether the system is vulnerable to
> CVE-2011-1898 due to the absence of interrupt remapping support.
> Although AMD iommus with interrupt remapping disabled are also affected,
> this case
> From: Xenia Ragiadakou
> Sent: Tuesday, January 24, 2023 8:42 PM
>
> Posted interrupt support in Xen is currently implemented only for the
> Intel platforms. Instead of calling directly pi_update_irte() from the
> common hvm code, add a pi_update_irte callback to the hvm_function_table.
> Then,
> From: Xenia Ragiadakou
> Sent: Tuesday, January 24, 2023 8:42 PM
>
> The function hvm_dpci_isairq_eoi() has no dependencies on VT-d driver
> code
> and can be moved from xen/drivers/passthrough/vtd/x86/hvm.c to
> xen/drivers/passthrough/x86/hvm.c, along with the corresponding
> copyrights.
>
>
> From: Jan Beulich
> Sent: Wednesday, February 1, 2023 5:30 PM
>
> On 01.02.2023 06:07, Tian, Kevin wrote:
> >> From: Xenia Ragiadakou
> >> Sent: Tuesday, January 24, 2023 8:42 PM
> >>
> >> The variable untrusted_msi indicates whether the syste
> From: Xenia Ragiadakou
> Sent: Monday, February 13, 2023 7:50 PM
>
> APIC virtualization support is currently implemented only for Intel VT-x.
> To aid future work on separating AMD-V from Intel VT-x code, instead of
> calling directly vmx_vlapic_msr_changed() from common hvm code, add a
> stub
> From: Roger Pau Monne
> Sent: Friday, May 20, 2022 9:38 PM
>
> Properly indent the handling of LBR enable in MSR_IA32_DEBUGCTLMSR
> vmx_msr_write_intercept().
>
> No functional change.
>
> Signed-off-by: Roger Pau Monné
Reviewed-by: Kevin Tian
> ---
> Feel free to squash onto the previous
> From: Roger Pau Monne
> Sent: Monday, June 27, 2022 6:01 PM
>
> The current logic in epte_get_entry_emt() will split any page marked
> as special with order greater than zero, without checking whether the
> super page is all special.
>
> Fix this by only splitting the page only if it's not all
> From: Roger Pau Monné
> Sent: Tuesday, June 28, 2022 8:52 PM
>
> On Thu, Jun 09, 2022 at 12:17:23PM +0200, Jan Beulich wrote:
> > Before actually enabling their use, provide a means to suppress it in
> > case of problems. Note that using the option can also affect the sharing
> > of page tables
> From: Roger Pau Monné
> Sent: Wednesday, June 29, 2022 5:11 PM
>
> On Wed, Jun 29, 2022 at 08:41:43AM +, Tian, Kevin wrote:
> > > From: Roger Pau Monne
> > > Sent: Monday, June 27, 2022 6:01 PM
> > >
> > > The current logic in epte_get
> From: Jane Malalane
> Sent: Wednesday, June 29, 2022 11:17 PM
>
> On 29/06/2022 15:26, Jan Beulich wrote:
> > On 29.06.2022 15:55, Jane Malalane wrote:
> >> Add XEN_SYSCTL_PHYSCAP_X86_ASSISTED_XAPIC and
> >> XEN_SYSCTL_PHYSCAP_X86_ASSISTED_X2APIC to report accelerated xAPIC
> and
> >> x2APIC, o
> From: Jane Malalane
> Sent: Wednesday, June 29, 2022 9:56 PM
>
> Introduce a new per-domain creation x86 specific flag to
> select whether hardware assisted virtualization should be used for
> x{2}APIC.
>
> A per-domain option is added to xl in order to select the usage of
> x{2}APIC hardware
> From: Jan Beulich
> Sent: Tuesday, July 5, 2022 8:45 PM
>
> Before actually enabling their use, provide a means to suppress it in
> case of problems. Note that using the option can also affect the sharing
> of page tables in the VT-d / EPT combination: If EPT would use large
> page mappings but
> From: Roger Pau Monne
> Sent: Friday, July 1, 2022 9:17 PM
>
> @@ -4065,6 +4065,11 @@ void vmx_vmexit_handler(struct cpu_user_regs
> *regs)
>
> if ( unlikely(exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) )
> return vmx_failed_vmentry(exit_reason, regs);
Add a blank line.
> +
> From: Roger Pau Monné
> Sent: Monday, July 4, 2022 6:07 PM
>
> On Mon, Jul 04, 2022 at 11:27:37AM +0200, Jan Beulich wrote:
> > On 01.07.2022 15:16, Roger Pau Monne wrote:
> > > --- a/xen/arch/x86/hvm/vmx/vmx.c
> > > +++ b/xen/arch/x86/hvm/vmx/vmx.c
> > > @@ -4065,6 +4065,11 @@ void vmx_vmexit_
> From: Roger Pau Monne
> Sent: Friday, July 1, 2022 9:17 PM
>
> @@ -225,6 +225,9 @@ static inline void pi_clear_sn(struct pi_desc *pi_desc)
>
> /*
> * Interruption-information format
> + *
> + * Note INTR_INFO_NMI_UNBLOCKED_BY_IRET is also used with Exit
> Qualification
> + * field under som
> From: Roger Pau Monne
> Sent: Friday, July 1, 2022 9:17 PM
> @@ -4589,6 +4601,22 @@ void vmx_vmexit_handler(struct cpu_user_regs
> *regs)
> */
> break;
>
> +case EXIT_REASON_NOTIFY:
> +__vmread(EXIT_QUALIFICATION, &exit_qualification);
> +
> +if ( exit_qua
> From: Jan Beulich
> Sent: Tuesday, February 28, 2023 5:52 PM
>
> Marking a DRHD as controlling an IGD isn't very sensible without
> checking that at the very least it's a graphics device that lives at
> :00:02.0. Re-use the reading of the class-code to control both the
> clearing of "gfx_on
> From: Marek Marczykowski-Górecki
> Sent: Tuesday, March 14, 2023 9:32 AM
>
> If the scope for IGD's IOMMU contains additional device that doesn't
> actually exist, iommu=no-igfx would not disable that IOMMU. In this
> particular case (Thinkpad x230) it included
> 00:02.1, but there is no such d
> From: Jan Beulich
> Sent: Friday, March 3, 2023 3:32 PM
>
> Switches of altp2m-s always expect a valid altp2m to be in place (and
> indeed altp2m_vcpu_initialise() sets the active one to be at index 0).
> The compiler, however, cannot know that, and hence it cannot eliminate
> p2m_get_altp2m()'
> From: Dmitry Isaykin
> Sent: Tuesday, March 21, 2023 9:59 PM
>
> Adds monitor support for I/O instructions.
>
> Signed-off-by: Dmitry Isaykin
> Signed-off-by: Anton Belousov
Reviewed-by: Kevin Tian
> From: Jan Beulich
> Sent: Tuesday, July 6, 2021 3:43 PM
>
> On 26.05.2021 10:19, Jan Beulich wrote:
> > IOMMU: make DMA containment of quarantined devices optional
> >
> > Containing still in flight DMA was introduced to work around certain
> > devices / systems hanging hard upon hitting a "not
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