Hi,
(answering to both Konrad and Bhupinder ...)
On 24/11/17 13:50, Konrad Rzeszutek Wilk wrote:
> On Fri, Nov 24, 2017 at 05:09:11PM +0530, Bhupinder Thakur wrote:
>> Currently, Xen supports only DT based initialization of 16550 UART.
>> This patch adds support for initializing 16550 UART using
Hi,
On 16/11/17 12:02, Andre Przywara wrote:
> If the host GICv3 redistributor reports that the pending table cannot
> use shareable memory, we try to drop the cacheability attributes as
> well. However we fail horribly in doing computer science 101 bit
> masking, effectively cleari
-by: Jann Horn
> Signed-off-by: Jan Beulich
Took me a while to wrap my head around it, because the actual fix is
just the "*cur_ref = 0;" line, I think.
But this looks correct to me.
Signed-off-by: Andre Przywara
> --- a/xen/common/grant_table.c
> +++ b/xen/common/gr
ince there is
only one caller, this might be overkill, though.
> Signed-off-by: Jan Beulich
Reviewed-by: Andre Przywara
Cheers,
Andre.
>
> --- a/xen/common/grant_table.c
> +++ b/xen/common/grant_table.c
> @@ -786,10 +786,10 @@ static int _set_status(unsigned gt_versi
>
Hi,
> And the most important question is how to recognize in Xen on ARM
> (using SCPI protocol) which frequencies are turbo-frequencies
> actually? I couldn't find any information regarding that in protocol
> description.
So traditionally on ARM there is no notion of a "turbo" frequency. Th
r of argument checks:
>>> We shouldn't accept zero-length elements with unknown bits set in "op".
>>> Also constify cache_flush()'s first parameter.
>>>
>>> Reported-by: Jann Horn
>>> Signed-off-by: Jan Beulich
>>
>> Took me
Hi,
On 10/11/17 16:42, Andre Przywara wrote:
> Hi,
>
> On 26/10/17 01:14, Stefano Stabellini wrote:
>> On Thu, 19 Oct 2017, Andre Przywara wrote:
>>> gic_clear_pending_irqs() was not only misnamed, but also misplaced, as
>>> a function solely dealing with the
Hi,
On 26/10/17 01:20, Stefano Stabellini wrote:
> On Thu, 19 Oct 2017, Andre Przywara wrote:
>> gic_remove_from_lr_pending() was not only misnamed, it also had the wrong
>> abstraction, as it should not live in gic.c.
>> Move it into vgic.c and vgic.h, where it belongs,
Hi,
On 26/10/17 01:37, Stefano Stabellini wrote:
> On Thu, 19 Oct 2017, Andre Przywara wrote:
>> Currently gic.c holds code to handle hardware IRQs as well as code to
>> bridge VGIC requests to the GIC virtualization hardware.
>
> That is true, however, I don't ne
gic_remove_irq_from_queues() was not only misnamed, it also has the wrong
abstraction, as it should not live in gic.c.
Move it into vgic.c and vgic.h, where it belongs to, and rename it on
the way.
Signed-off-by: Andre Przywara
Reviewed-by: Stefano Stabellini
---
xen/arch/arm/gic.c
In event.h we very deeply dive into the VGIC to learn if an event for
a guest is pending.
Rework that function to abstract the VGIC specific part out. Also
reorder the queries there, as we only actually need to check for the
event channel if there are no other pending IRQs.
Signed-off-by: Andre
Currently gic_dump_info() not only dumps the hardware state of the GIC,
but also the VGIC internal virtual IRQ lists.
Split the latter off and move it into gic-vgic.c to observe the abstraction.
Signed-off-by: Andre Przywara
---
xen/arch/arm/domain.c | 1 +
xen/arch/arm/gic-vgic.c | 11
ll be addressed later.
Andre Przywara (10):
ARM: remove unneeded gic.h inclusions
ARM: vGIC: fix nr_irq definition
ARM: VGIC: move gic_remove_irq_from_queues()
ARM: VGIC: streamline gic_restore_pending_irqs()
ARM: VGIC: split gic.c to observe hardware/virtual GIC separation
ARM:
At the moment we happily access the VGIC internal struct pending_irq
(which describes a virtual IRQ) in irq.c.
Factor out the actually needed functionality to learn the associated
hardware IRQ and move that into gic-vgic.c to improve abstraction.
Signed-off-by: Andre Przywara
Acked-by: Stefano
-off-by: Andre Przywara
---
xen/arch/arm/domain.c | 1 +
xen/arch/arm/gic.c| 11 +--
xen/arch/arm/traps.c | 2 +-
xen/include/asm-arm/gic.h | 2 +-
4 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
index
as
a local variable name or as a function parameter.
Drop the optimization and make nr_irqs a normal variable for ARM also.
Signed-off-by: Andre Przywara
Reviewed-by: Stefano Stabellini
---
xen/arch/arm/irq.c| 2 ++
xen/include/asm-arm/irq.h | 2 +-
2 files changed, 3 insertions(+), 1 del
actually
not needed.
Signed-off-by: Andre Przywara
Reviewed-by: Stefano Stabellini
---
xen/arch/arm/domain_build.c | 1 -
xen/arch/arm/p2m.c | 1 -
xen/arch/arm/platforms/vexpress.c| 1 -
xen/arch/arm/platforms/xgene-storm.c | 1 -
xen/arch/arm/time.c
separate file,
so that gic.c does what is says on the tin.
Signed-off-by: Andre Przywara
---
xen/arch/arm/Makefile | 1 +
xen/arch/arm/gic-vgic.c | 413
xen/arch/arm/gic.c | 366 +-
3 files changed, 416
The functions to actually populate a list register were accessing
the VGIC internal pending_irq struct, although they should be abstracting
from that.
Break the needed information down to remove the reference to pending_irq
from gic-v[23].c.
Signed-off-by: Andre Przywara
---
xen/arch/arm/gic-v2
said accesses to VGIC data structures and improves abstraction.
Signed-off-by: Andre Przywara
Acked-by: Stefano Stabellini
---
xen/arch/arm/gic-vgic.c| 31 +++
xen/arch/arm/gic.c | 42 ++
xen/include/asm-arm/vgic.h | 2
Hi,
On 26/10/17 09:28, Julien Grall wrote:
> Hi Andre,
>
> On 10/19/2017 01:48 PM, Andre Przywara wrote:
>> The functions to actually populate a list register were accessing
>> the VGIC internal pending_irq struct, although they should be abstracting
>> from that.
>
Hi,
On 08/12/17 10:56, George Dunlap wrote:
> On 12/07/2017 07:21 PM, Marc Zyngier wrote:
>> On 07/12/17 18:06, George Dunlap wrote:
>>> On 12/07/2017 04:58 PM, Marc Zyngier wrote:
On 07/12/17 16:44, George Dunlap wrote:
> On 12/07/2017 04:04 PM, Julien Grall wrote:
>> Hi Jan,
>>
On Thu, 16 May 2019 17:15:36 +0530
Amit Tomer wrote:
Hi,
> Thanks for having a look at it.
>
> On Thu, May 16, 2019 at 12:25 AM Oleksandr wrote:
> >
> >
> > On 03.05.19 20:02, Amit Singh Tomar wrote:
> >
> > Hi, Amit
> >
> > > XEN should not forward PPIs to Dom0 as it only support SPIs.
> >
On Tue, 28 May 2019 18:07:19 +0100
Julien Grall wrote:
[ ... ]
> While looking at the code, I noticed that in the new vgic vgic_get_irq()
> looks unsafe to be called with interrupt unmasked. This is because one
> of the callee (vgic_get_lpi()) takes a spinlock and not a spinlock_irq.
> Andre,
On Fri, 31 May 2019 18:16:52 +0100
Julien Grall wrote:
> Hi,
>
> On 30/05/2019 17:14, Andrii Anisov wrote:
> >
> >
> > On 29.05.19 18:32, Julien Grall wrote:
> >>> BTW, do you hear about plans for the new vgic? Some time ago it was said
> >>> that
> >>> new vgic implementation going to rep
; disconnection on debug builds.
>
> Fixes: ec2a2f1 ("ARM: VGIC: factor out vgic_connect_hw_irq()")
> Signed-off-by: Andrii Anisov
> Suggested-by: Stefan Nuernberger
Reviewed-by: Andre Przywara
Cheers,
Andre.
> ---
> in v2:
> - updated condition as suggeste
8250/16550 driver for the aux UART [2].
>
> Unfortunately the brcm,bcm2835-aux-uart device tree binding doesn't
> have the reg-shift and reg-io-width properties [3]. Thus, the reg-shift
> and reg-io-width properties are inherent properties of this UART.
>
> Thanks to Andre Przywa
On Wed, 31 Jul 2019 12:02:20 +0100
Julien Grall wrote:
Hi,
> On 30/07/2019 18:35, Andrii Anisov wrote:
> >
> > On 26.07.19 13:59, Julien Grall wrote:
> >> Hi,
> >>
> >> On 26/07/2019 11:37, Andrii Anisov wrote:
> >>> From: Andrii Anisov
> >>>
> >>> On ARM64 we know exactly if trap happened
On Mon, 29 Jul 2019 09:19:18 -0400
Stewart Hildebrand wrote:
Hi,
> This is a series to enable UART console for Raspberry Pi 4. Note that I'm
> relying on the firmware to initialize the UART (i.e. enable_uart=1 in
> config.txt), since full UART initialization on this platform requires
> access
On Mon, 15 Apr 2019 13:41:41 +0530
Amit Tomer wrote:
> Hello,
>
> > After talking via IRC, the problem is PPIs, that this platform uses for
> > PMU interrupts. When Xen tries to setup the IRQ forwarding for Dom0 for
> > this device, it fails because it only supports forwarding SPIs.
> > So inter
e memory map, they missed the opportunity to put each device at
least in their own 4K page.
Reviewed-by: Andre Przywara
If you can wait till this evening, I can even test it.
It's actually a shame that we need this enumeration, when all we are after is
an answer to the question: Does a d
On Tue, 3 Dec 2019 16:52:45 +
Julien Grall wrote:
Hi,
> On 03/12/2019 14:38, Andre Przywara wrote:
> > On Tue, 3 Dec 2019 11:39:58 +
> > Julien Grall wrote:
> >
> > Hi,
> >
> >> (+Andre)
> >>
> >> Hi,
> >>
>
On Mon, 11 Nov 2019 11:01:07 -0800 (PST)
Stefano Stabellini wrote:
Hi,
> On Sat, 9 Nov 2019, Julien Grall wrote:
> > On Sat, 9 Nov 2019, 04:27 Stefano Stabellini,
> > wrote:
> > On Thu, 7 Nov 2019, Peng Fan wrote:
> > > The end should be GICD_ISACTIVERN not GICD_ISACTIVER.
> >
On Thu, 29 Nov 2018 07:40:00 +
Andrii Anisov wrote:
> Hello,
>
> Again, I sent this cover letter only to myself. So, here it is, hope
> it does not break the thread. Sorry for the mess.
>
>
> From: Andrii Anisov
> Sent: Wednesday, November 28, 2018 11:31 PM
> Cc: Andrii Anisov
> Subject:
On Wed, 28 Nov 2018 23:31:57 +0200
Andrii Anisov wrote:
Hi,
> From: Andrii Anisov
>
> This reduces some code and conditions in an IRQ processing path,
> and opens way to further code reduction.
While I understand that this is some sort of a hack, I am commenting
just on this patch to demonstr
On Wed, 28 Nov 2018 23:32:05 +0200
Andrii Anisov wrote:
Hi,
> From: Andrii Anisov
>
> All bit operations for gic, vgic and gic-vgic are performed under
> spinlocks, so there is no need for atomic bit ops here, they only
> introduce excessive call to functions used more expensive exclusive
> AR
On 30/11/2018 19:52, Andrii Anisov wrote:
> Hello Andre,
>
> Please see my comments below:
>
> On 23.11.18 14:18, Andre Przywara wrote:
>> Fundamentally there is a semantic difference between edge and level
>> triggered IRQs: When the guest has handled an *edge* IRQ
On Mon, 3 Dec 2018 14:33:08 +0200
Andrii Anisov wrote:
Hi Andrii,
> On 29.11.18 14:14, Andre Przywara wrote:
> > Nah, please don't do this.
> Sorry for making you crying looking at this code.
> It's terrible, I know. It's rather an idea.
>
> >
Hi,
On 04/04/18 01:04, Stefano Stabellini wrote:
> On Tue, 3 Apr 2018, Julien Grall wrote:
>> On 29/03/18 18:35, Stefano Stabellini wrote:
>>> On Thu, 29 Mar 2018, Andre Przywara wrote:
>>>> Stefano pointed out the following situation:
>>>> --
Hi,
On 03/04/18 14:49, Amit Singh Tomar wrote:
> Signed-off-by: Amit Singh Tomar
> ---
> Changes since v1:
> * Removed header file dependency.
>
> ---
> docs/misc/arm/early-printk.txt | 1 +
> xen/arch/arm/Rules.mk | 1 +
> xen/arch/arm/arm64/debug-mvebu.inc
Hi,
one more thing ...
On 04/04/18 16:34, Andre Przywara wrote:
> Hi,
>
> On 03/04/18 14:49, Amit Singh Tomar wrote:
>> diff --git a/xen/arch/arm/arm64/debug-mvebu.inc
>> b/xen/arch/arm/arm64/debug-mvebu.inc
>> new file mode 100644
>> index 000..ac48
Hi,
On 03/04/18 14:49, Amit Singh Tomar wrote:
> This patch adds driver for UART controller found on Armada 3700 SoC.
>
> There is no reference manuals available for 3700 SoC in public and it
> is derived by looking at Linux driver[1].
>
> [1]https://github.com/torvalds/linux/blob/master/drivers
Hi,
On 05/04/18 11:16, Amit Singh Tomar wrote:
> Signed-off-by: Amit Singh Tomar
Reviewed-by: Andre Przywara
Cheers,
Andre.
> ---
> Changes since v2:
> * Addressed Andre's comments.
> Changes since v1:
> * Removed header file dependency.
> ---
> d
gt; +{
> +struct mvebu3700_uart *uart = port->uart;
> +uint32_t reg;
> +
> +reg = mvebu3700_read(uart, UART_CTRL_REG);
> + reg &= ~CTRL_TX_RDY_INT;
> +mvebu3700_write(uart, UART_CTRL_REG, reg);
> +}
> +
> +static void mvebu3700_uart_start_tx(stru
/linux/blob/master/drivers/tty/serial/mvebu-uart.c
> commit-id: c685af1108d7c303f0b901413405d68eaeac4477
>
> Signed-off-by: Amit Singh Tomar
Reviewed-by: Andre Przywara
Tested-by: Andre Przywara
Cheers,
Andre.
> ---
> Changes since v3:
> * Dropped uart->irq >
Hi,
On 28/04/18 10:08, Amit Singh Tomar wrote:
> While working on MVEBU uart driver, Julien pointed out that (uart->irq > 0)
> check is unnecessary during irq set up.if ever there is an invalid irq, driver
> initialization itself would be bailed out from platform_get_irq.
>
> This patch would rem
Instead of hard coding the architected redistributor stride into the
code, lets use a clear #define to the two values for GICv3 and GICv4 and
clarify the algorithm to determine the needed stride value.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- no changes
xen/arch/arm/gic-v3.c
structures.
Move this function into vgic.c, to keep this VGIC internal.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- dump previous approach, move function to VGIC specific file instead
xen/arch/arm/domain.c | 14 --
xen/arch/arm/vgic.c | 14 ++
2 files changed, 14
esses
- use interface for HCR bit changes
- iterate over set CPU bits in SGI injection handler
Andre Przywara (57):
tools: ARM: vGICv3: Avoid inserting optional DT properties
ARM: vGICv3: clarify on GUEST_GICV3_RDIST_REGIONS symbol
ARM: GICv3: use hardware GICv3 redistributor values for
definition of these
embedded structures into vgic.h, and just use the opaque type in the arch
specific structures.
This allows easy switching between different implementations later.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- No changes
xen/include/asm-arm/domain.h | 85
Currently vgic.h both contains prototypes used by Xen arch code outside
of the actual VGIC (for instance vgic_vcpu_inject_irq()), and prototypes
for functions used by the VGIC internally.
Group them to later allow an easy split with one #ifdef.
Signed-off-by: Andre Przywara
Reviewed-by: Julien
: Andre Przywara
---
Changelog RFC ... v1:
- new patch
xen/arch/arm/gic-v2.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c
index 7938a42591..618dd94120 100644
--- a/xen/arch/arm/gic-v2.c
+++ b/xen/arch/arm/gic-v2.c
state of
an associated hardware IRQ.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- use struct irq_desc* in the interface (instead of just the IRQ number)
- add set_pending_state() (needed later)
xen/arch/arm/gic-v2.c | 32
xen/arch/arm/gic-v3.c
don't need to describe them if they don't differ from the
default values. This will always be the case for our constructed
DomU memory map.
So we drop those properties altogether and provide a clean and architected
GICv3 DT node for DomUs.
Signed-off-by: Andre Przywara
---
Changelog
clude file, nothing has been changed in this code.
This is based on Linux commit 8e4447457965, written by Christoffer Dall.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- use Linux coding style for list_sort.c
xen/arch/arm/vgic/vgic.c| 59 +
xen/common/list_s
Marc Zyngier.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- adapt to former changes
- whitespace fixes
- use C99 data types
- drop unneeded regions support (ITS, CPU i/f)
xen/arch/arm/vgic/vgic-mmio.c | 180 ++
xen/arch/arm/vgic/vgic-mmio.h
The config register handlers are shared between the v2 and v3 emulation,
so their implementation goes into vgic-mmio.c, to be easily referenced
from the v3 emulation as well later.
This is based on Linux commit 79717e4ac09c, written by Andre Przywara.
Signed-off-by: Andre Przywara
---
Changelog
heir usage in gic-v3.c
and is needed to allow co-existence of the GICv2 and GICv3 definitions
in the same file.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- new patch
xen/arch/arm/gic-v3.c | 48 +++---
xen/include/asm-ar
ity in the new kick_vcpu() function
and make this available to the whole Xen arch code.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- new patch
xen/arch/arm/smp.c| 14 ++
xen/arch/arm/vgic.c | 10 ++
xen/include/asm-arm/smp.h | 3 +++
3 files c
So far the number of list registers (LRs) a GIC implements is only
needed in the hardware facing side of the VGIC code (gic-vgic.c).
The new VGIC will need this information in more and multiple places, so
export a function that returns the number.
Signed-off-by: Andre Przywara
---
Changelog RFC
a hardware mapped vIRQ on the way.
This is based on Linux commit 2c234d6f1826, written by Andre Przywara.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- propagate affinity changes to hardware mapped IRQs
xen/arch/arm/vgic/vgic-mmio-v2.c | 64
The bit definition for the CPUID mask in the GICv2 LR register was
wrong, fortunately the current implementation does not use that bit.
Fix it up (it's starting at bit 10, not bit 9) and clean up some
nearby definitions on the way.
This will be used by the new VGIC shortly.
Signed-off-by:
Tell Xen whether a particular VCPU has an IRQ that needs handling
in the guest. This is used to decide whether a VCPU is runnable or
if a hypercall should be preempted to let the guest handle the IRQ.
This is based on Linux commit 90eee56c5f90, written by Eric Auger.
Signed-off-by: Andre
gic_event_needs_delivery() is not named very intuitively, especially
the gic_ prefix is somewhat misleading.
Rename it to vgic_pending_irq(), which makes it clear that this relates
to the virtual GIC and is about interrupts.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- new patch
The ARM arch code requires an interrupt controller emulation to implement
vgic_clear_pending_irqs(), although it is suspected that it is actually
not necessary. Go with a stub for now to make the linker happy.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- split off from former patch
can't
easily reuse the existing implementation.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- no changes
xen/arch/arm/vgic/vgic.c | 44
1 file changed, 44 insertions(+)
diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/v
When a VCPU moves to another CPU, we need to adjust the target affinity
of any hardware mapped vIRQs, to observe our "physical-follows-virtual"
policy.
Implement arch_move_irqs() to adjust the physical affinity of all hardware
mapped vIRQs targetting this VCPU.
Signed-off-by: Andr
in pointless MMIO reads for many registers.
Add an option to gicv3_poke_irq() to state whether we want to wait for
this bit and use it accordingly to match the spec.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- new patch
xen/arch/arm/gic-v3.c | 12 +++-
1 file changed, 7
assemble those bits from/to an LR.
This allows the new VGIC to use this information.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- new patch
xen/arch/arm/gic-v2.c | 7 +++
xen/include/asm-arm/gic.h | 8 +---
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/xen
oment.
This is based on Linux commit dd238ec2b87b, written by Andre Przywara.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- use 32 bit register types
xen/arch/arm/vgic/vgic-mmio-v2.c | 2 +-
xen/arch/arm/vgic/vgic-mmio.c| 47
xen/arch/arm/vgic
n the moment this is restricted to a vGIC-v2. To make the build system
happy, we provide a temporary dummy implementation of
vgic_v3_setup_hw() to allow building for now.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- no changes
xen/arch/arm/Kconfig | 6 +-
xen/arch/
setup the host GIC addresses.
This is based on Linux commit 140b086dd197, written by Marc Zyngier.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- extend comments
- adapt to former changes
- use existing Xen LR accessor interface (->write_lr, ->read_lr)
- merge save_state and re
prepares the callers
to do the right thing later automatically.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- no change
xen/arch/arm/domain.c | 4 ++--
xen/arch/arm/gic-v3-lpi.c | 2 +-
xen/arch/arm/irq.c | 2 +-
xen/arch/arm/time.c| 2 +-
xen/arch/ar
value.
Signed-off-by: Andre Przywara
Acked-by: Julien Grall
---
Changelog RFC ... v1:
- Add Julien's ACK
xen/arch/arm/gic-v3.c | 3 +--
xen/arch/arm/vgic-v3.c| 14 --
xen/include/asm-arm/domain.h | 1 -
xen/include/asm-arm/vgic.h| 1 -
xen/include/p
combine it with the
device's level to get the actual pending state.
Hardware mapped IRQs need some special handling, as their hardware state
has to be coordinated with the virtual pending bit to avoid hanging
or masked interrupts.
This is based on Linux commit 96b298000db4, written by Andre Prz
dware domain.
This avoids the hardware GIC code to reference vGIC data structures.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- Use GIC hardware values consistently in this function.
xen/arch/arm/gic-v3.c | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff
The emulated ARM SBSA UART is using level triggered IRQ semantics,
however the current VGIC can only handle edge triggered IRQs, really.
Disable the existing workaround for this problem in case we have the
new VGIC in place, which can properly handle level triggered IRQs.
Signed-off-by: Andre
Normally there is only one GICv3 redistributor region, and we use
that for DomU guests using a GICv3.
Explain the background in a comment and why we need to keep the number
of hardware regions for Dom0.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- Keep GUEST_GICV3_RDIST_REGIONS
Triggering an IPI via this register is v2 specific, so the
implementation lives entirely in vgic-mmio-v2.c.
This is based on Linux commit 55cc01fb9004, written by Andre Przywara.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- use symbolic names instead of magic values
- iterates over
to avoid touching all the users.
This is based on Linux commit b18b57787f5e, written by Christoffer Dall.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- rename header file to new_vgic.h
- drop unneeded data structures (vgic_its, vgic_v_cpu_if)
- reorder members in vgic_irq to avoid
pending state of a
particular interrupt. Due to hardware limitations this only works for
private interrupts of the current CPU, so there is no CPU field in the
prototype.
This adds gicv2/3_peek_irq() helper functions, to read a bit in a bitmap
spread over several MMIO registers.
Signed-off-by: Andre
This patch implements the function which is called by Xen when it wants
to register the virtual GIC.
This also implements domain_max_vcpus() for the new VGIC, which reports
back the maximum number of VCPUs a certain GIC model supports.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1
, so chances are we are tasked to clear bits that are already zero.
Add some simple check to avoid a pointless warning in this case.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- remove premature "proper ACTIVE" handler stub
- avoid unnecessary warnings on NO-OP register write
.
This is based on Linux commit 2b0cda878965, written by Marc Zyngier.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- use PRODUCT_ID_XEN
- use proper locking on enabling VGIC
- use kick_vcpu()
xen/arch/arm/vgic/vgic-mmio-v2.c | 54 +++-
xen/arch/arm/vgic
there is no real technical
reason this struct has to fit in one page, so lifting the limit to two
pages seems like the most pragmatic solution.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- no changes
xen/arch/arm/domain.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
-by: Andre Przywara
---
Changelog RFC ... v1:
- adapting to previous changes
xen/arch/arm/vgic/vgic-v2.c | 66 +
xen/arch/arm/vgic/vgic.h| 1 +
2 files changed, 67 insertions(+)
diff --git a/xen/arch/arm/vgic/vgic-v2.c b/xen/arch/arm/vgic/vgic-v2.c
The Xen core/arch code relies on two abstracted functions to inject an
event channel IRQ and to query its pending state.
Implement those to query the state of the new VGIC implementation.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- add locking
xen/arch/arm/vgic/vgic.c | 23
.
Because the existing locking order between vgic_irq->irq_lock and
irq_desc->lock dictates so, we drop the irq_lock and retake them in the
proper order.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- extend and move vgic_sync_hardware_irq()
- do proper locking sequence
- skip a
When we dump guest state on the Xen console, we also print the state of
IRQs that are on a VCPU.
Add the code to dump the state of an IRQ handled by the new VGIC.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- use proper locking
- use one header line to announce active or pending IRQs
vGIC (and the LR).
The VGIC in Xen so far only implemented edge triggered vIRQs, really, so
we need to add new functionality to re-sample the interrupt state.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- extend comments
- don't read CNTV_CVAL_EL0
- use symbolic names for constants
ed in the
following patches.
This is based on Linux commit 0919e84c0fc1, written by Marc Zyngier.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- extend comments
- adapt to former changes
- remove gic_clear_lrs()
xen/arch/arm/vgic/vgic.c
initialize the VGIC.
Their prototypes are already in existing header files.
This is based on Linux commit ad275b8bb1e6, written by Eric Auger.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- adapt to former changes
- add missing comment line
- extend commit message
xen/arch/arm/vgic
Enable the VGIC operation by properly initialising the registers
in the hypervisor GIC interface.
This is based on Linux commit f7b6985cc3d0, written by Eric Auger.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- drop unneeded vgic_vmcr initialization
- use update_hcr_status wrapper
physical world.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- add ASSERT for hardware mapped IRQs being SPI only
- check h/w IRQ matches before disconnecting
xen/arch/arm/vgic/vgic.c | 71
1 file changed, 71 insertions(+)
diff --git a/xen
patch.
This is based on Linux commit 81eeb95ddbab, written by Christoffer Dall.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- fix locking order comment
- adapt to former changes
- extend comments
- use kick_vcpu()
xen/arch/arm/vgic/vgic.c
As this register is v2 specific, its implementation lives entirely
in vgic-mmio-v2.c.
This register allows setting the source mask of an IPI.
This is based on Linux commit ed40213ef9b0, written by Andre Przywara.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- use C99 and unsigned
interrupts and SPIs, but handles the ref-counting for LPIs.
This is based on Linux commit 64a959d66e47, written by Christoffer Dall.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- add kernel-doc comments to exported functions
- adapt to previous changes (new_vgic.h, arch_vcpu member name
The two central functions to synchronise our emulated VGIC state with
the GIC hardware (the LRs, really), are named somewhat confusingly.
Rename them from gic_inject() to vgic_sync_to_lrs() and from
gic_clear_lrs() to vgic_sync_from_lrs(), to make the code more readable.
Signed-off-by: Andre
on Linux commit fb848db39661, written by Andre Przywara.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- drop (dummy) user interface entries
- use frame number instead of physical address
xen/arch/arm/vgic/vgic-mmio-v2.c | 83
xen/arch/arm/vgic
evtchn_upcall_pending variable to make the interrupt
line match its status, and call this function upon every hypervisor
entry.
Signed-off-by: Andre Przywara
---
Changelog RFC ... v1:
- no changes
xen/arch/arm/domain.c | 7 +++
xen/arch/arm/traps.c| 1 +
xen/include/asm-arm/event.h
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