On Mon, Jul 7, 2025 at 5:04 PM Jan Beulich wrote:
>
> On 07.07.2025 17:51, Frediano Ziglio wrote:
> > On Mon, Jul 7, 2025 at 4:42 PM Jan Beulich wrote:
> >>
> >> On 07.07.2025 17:11, Frediano Ziglio wrote:
> >>> EFI code path split options from EFI LoadOptions fields in 2
> >>> pieces, first EFI
This is a small add-on series after the live-update series sent a week
ago.
I realized that having the shared info page in the normal RAM area is
a bad idea when considering kexec, as the new kernel might want it at
a different location.
So this series is moving the shared info page away from the
On 07.07.2025 19:31, Sergii Dmytruk wrote:
> On Mon, Jul 07, 2025 at 10:29:46AM +0200, Jan Beulich wrote:
... then isn't used right here, instead requiring a cast somewhere
(presumably,
as code using this isn't visible in this patch).
>>>
>>> As was mentioned earlier: because size o
[Public]
> -Original Message-
> From: Jan Beulich
> Sent: Tuesday, June 17, 2025 6:38 PM
> To: Penny, Zheng
> Cc: Huang, Ray ; Anthony PERARD
> ; Andrew Cooper ;
> Orzel, Michal ; Julien Grall ; Roger Pau
> Monné ; Stefano Stabellini ;
> xen-
> de...@lists.xenproject.org
> Subject: Re:
On 7/7/25 20:07, Stefano Stabellini wrote:
> Today, checking for non-fatal MCE errors on ARM is very invasive: it
s/ARM/AMD/
--
Sincerely,
Demi Marie Obenour (she/her/hers)
OpenPGP_0xB288B55FFF9C22C1.asc
Description: OpenPGP public key
OpenPGP_signature.asc
Description: OpenPGP digital signatu
On 06.07.2025 18:55, Sergii Dmytruk wrote:
> On Wed, Jul 02, 2025 at 04:36:27PM +0200, Jan Beulich wrote:
>> On 30.05.2025 15:17, Sergii Dmytruk wrote:
>>> The file provides constants, structures and several helper functions for
>>> parsing SLRT.
>>>
>>> The data described by the structures is pass
On 06.07.2025 19:34, Sergii Dmytruk wrote:
> On Wed, Jul 02, 2025 at 04:57:12PM +0200, Jan Beulich wrote:
>>> @@ -440,9 +436,10 @@ static DEFINE_SPINLOCK(set_atomicity_lock);
>>> * has been called.
>>> */
>>>
>>> -static bool prepare_set(void)
>>> +struct mtrr_pausing_state mtrr_pause_caching(v
On 02/07/2025 16:13, Hari Limaye wrote:
> From: Penny Zheng
>
> Introduce map_pages_to_xen() that is implemented using a new helper,
> xen_mpumap_update(), which is responsible for updating Xen MPU memory
> mapping table(xen_mpumap), including creating a new entry, updating
> or destroying an
On 04.07.2025 22:39, Dmytro Prokopchuk1 wrote:
> Address a violation of MISRA C:2012 Rule 5.5:
> "Identifiers shall be distinct from macro names".
>
> Reports for service MC3A2.R5.5:
> xen/include/xen/iommu.h: non-compliant struct 'page_list_head'
> xen/include/xen/mm.h: non-compliant macro 'page_
Introduce support for IRQ setup on RISC-V by implementing setup_irq() and
__setup_irq(), adapted and extended from an initial implementation by [1].
__setup_irq() does the following:
- Sets up an IRQ action.
- Validates that shared IRQs have non-NULL `dev_id` and are only used when
existin
The patch series introduces basic UART support (in interrupt mode) and support
of
interrupts for hypervisor mode.
To implement this the following has been added:
- APLIC and IMISC initialization.
- Introduce of intc_hw_operations abstraction.
- Introduce some APLIC and IMSIC operations.
- Introdu
Introduce interrupt controller descriptor for host APLIC to describe
the low-lovel hardare. It includes implementation of the following functions:
- aplic_irq_startup()
- aplic_irq_enable()
- aplic_irq_disable()
- aplic_set_irq_affinity()
As APLIC is used in MSI mode it requires to enable/disa
Introduce intc_init() to initialize the interrupt controller using the
registered hardware ops.
Also add intc_route_irq_to_xen() to route IRQs to Xen, with support for
setting IRQ type and priority via new internal helpers intc_set_irq_type()
and intc_set_irq_priority().
Call intc_init() to do bas
imsic_init() is introduced to parse device tree node, which has the following
bindings [2], and based on the parsed information update IMSIC configuration
which is stored in imsic_cfg.
The following helpers are introduces for imsic_init() usage:
- imsic_parse_node() parses IMSIC node from DTS
Implement functions necessarry to have working external interrupts in
hypervisor mode. The following changes are done:
- Add a common function intc_handle_external_irq() to call APLIC specific
function to handle an interrupt.
- Update do_trap() function to handle IRQ_S_EXT case; add the che
aplic_init() function does the following few things:
- checks that IMSIC in device tree node ( by checking msi-parent property
in APLIC node ) is present as current one implmenetaion of AIA is
supported only MSI method.
- initialize IMSIC based on IMSIC device tree node
- Read value of AP
Update Kconfig to select GENERIC_UART_INIT for basic UART init ( find a dt node
and call device specific device_init() ).
Drop `default n if RISCV` statement for config HAS_NS16550 as now ns16550 is
ready to be compiled and used by RISC-V. Also, make the config user selectable
for everyone except
On 07.07.2025 13:46, Oleksii Kurochko wrote:
> On 7/7/25 9:20 AM, Jan Beulich wrote:
>> On 04.07.2025 17:01, Oleksii Kurochko wrote:
>>> On 7/1/25 3:49 PM, Jan Beulich wrote:
On 10.06.2025 15:05, Oleksii Kurochko wrote:
> This patch introduces p2m_set_entry() and its core helper
> __p
On 05.07.2025 01:48, Petr Beneš wrote:
> On Wed, Jul 2, 2025 at 9:15 AM Jan Beulich wrote:
>>
>> On 02.07.2025 01:45, Petr Beneš wrote:
>>> From: Petr Beneš
>>
>> This isn't in line with the first S-o-b, nor with the fact that in the cover
>> letter you say this was previously submitted (and henc
On 05.07.2025 16:27, Koichiro Den wrote:
> --- a/xen/include/xen/macros.h
> +++ b/xen/include/xen/macros.h
> @@ -5,6 +5,7 @@
> #define ROUNDDOWN(x, a) ((x) & ~((a) - 1))
>
> #define IS_ALIGNED(val, align) (!((val) & ((align) - 1)))
> +#define IS_POWER_OF_TWO(val) ((val) && !((val) & ((val) -
On 06.07.2025 23:55, Sergii Dmytruk wrote:
> On Wed, Jul 02, 2025 at 05:11:26PM +0200, Jan Beulich wrote:
>> On 30.05.2025 15:17, Sergii Dmytruk wrote:
>>> @@ -442,6 +444,9 @@ static uint64_t __init mtrr_top_of_ram(void)
>>> ASSERT(paddr_bits);
>>> addr_mask = ((1ULL << paddr_bits) - 1) &
On Mon, Jun 23, 2025 at 06:19:27PM -0700, Stefano Stabellini wrote:
> diff --git a/xen/include/xen/compile.h.in b/xen/include/xen/compile.h.in
> index 3151d1e7d1..9206341ba6 100644
> --- a/xen/include/xen/compile.h.in
> +++ b/xen/include/xen/compile.h.in
> @@ -1,3 +1,6 @@
> +#ifndef XEN_COMPILE_H
>
On 07/07/2025 13:56, Hari Limaye wrote:
> Hi Michal,
>
>> On Fri, Jul 04, 2025 at 09:54:28AM +, Michal Orzel wrote:
>> When CONFIG_PDX_COMPRESSION=n, pdx_init_mask(), pdx_region_mask() and
>> pfn_pdx_hole_setup() are just stubs doing nothing. It does not make
>> sense to keep the two loops
On 01.07.2025 21:54, Petr Beneš wrote:
> --- a/tools/libs/light/libxl_create.c
> +++ b/tools/libs/light/libxl_create.c
> @@ -421,6 +421,15 @@ int libxl__domain_build_info_setdefault(libxl__gc *gc,
> return -ERROR_INVAL;
> }
>
> +if (b_info->altp2m_count == LIBXL_ALTP2M_COUNT_DEF
We're generally striving to minimize behavioral differences between PV
and PVH Dom0. Using (just?) is_memory_hole() in the PVH case looks quite
a bit weaker to me, compared to the page ownership check done in the PV
case. Extend checking accordingly.
Signed-off-by: Jan Beulich
---
The addition ma
On Thu Jul 3, 2025 at 8:04 AM CEST, Jan Beulich wrote:
> On 02.07.2025 17:34, Alejandro Vallejo wrote:
>> On Wed Jul 2, 2025 at 5:15 PM CEST, Jan Beulich wrote:
>>> On 02.07.2025 17:09, Alejandro Vallejo wrote:
On Wed Jul 2, 2025 at 3:15 PM CEST, Jan Beulich wrote:
> On 01.07.2025 12:56, A
On Mon, Jul 7, 2025 at 3:35 PM Anthony PERARD wrote:
>
> It seems that altp2m_count is going to be used for the creation of all
> guest, right? That is in addition to HVM, it will be also used for PV
> guest and on Arm, and any other architectures that could be added.
>
> Anthony PERARD
I'm sugge
On Tue, Jul 01, 2025 at 07:54:24PM +, Petr Beneš wrote:
> diff --git a/tools/libs/light/libxl_create.c b/tools/libs/light/libxl_create.c
> index 8a85fba1cf..acf7fd9837 100644
> --- a/tools/libs/light/libxl_create.c
> +++ b/tools/libs/light/libxl_create.c
> @@ -421,6 +421,15 @@ int libxl__domain
On Tue, Jul 01, 2025 at 03:11:39PM +0300, Mykola Kvach wrote:
> On Fri, Jun 27, 2025 at 3:37 PM Anthony PERARD wrote:
> > On Thu, Jun 26, 2025 at 11:12:46AM +0300, Mykola Kvach wrote:
> > > Both scenarios are rare and typically require very small watchdog
> > > timeouts combined with significant d
On 04.07.2025 17:01, Oleksii Kurochko wrote:
> On 7/1/25 3:49 PM, Jan Beulich wrote:
>> On 10.06.2025 15:05, Oleksii Kurochko wrote:
>>> This patch introduces p2m_set_entry() and its core helper __p2m_set_entry()
>>> for
>>> RISC-V, based loosely on the Arm implementation, with several
>>> RISC-V
On 04.07.2025 22:39, Dmytro Prokopchuk1 wrote:
> Address a violation of MISRA C:2012 Rule 5.5:
> "Identifiers shall be distinct from macro names".
>
> Reports for service MC3A2.R5.5:
> xen/include/xen/irq.h: non-compliant function `pirq_cleanup_check(struct
> pirq*, struct domain*)'
> xen/include
From: Oleksandr Tyshchenko
Program PCIE BDF-OSID assignment according to the S4_PCIe_IPMMU-OSID
when adding PCI device to the IOMMU in ipmmu_add_device callback.
This is needed for being able to assign PCI devices to different
domains at the same time. Programmed OSID is emmited as sideband data
This series introduces IPMMU handling for PCIe passthrough on ARM. It includes
changes to pci-designware, pci-host-rcar and ipmmu-vmsa drivers to enable
configuring BDF->OSID->uTLB translation chain needed to pass different PCIe
devices to different domains.
Tested on RCar S4 Spider board.
Mykyta
For IPMMU to be able to associate a specific PCI device with it's TLB
the BDF to OSID mapping needs to be set up in the host bridge. The
configured OSID is then emmited as a sideband data on the AXI bus during
PCI DMA transactions. OSID configuration registers are located in the
"app" region of the
Introduce an additional private data field in `dw_pcie_priv` to allow
vendors to store custom data without interfering with bridge->priv.
Also add get/set pair to make accesing that private data less
cumbersome.
Signed-off-by: Mykyta Poturai
---
xen/arch/arm/pci/pci-designware.c | 12 +++
Hi Michal,
> On Fri, Jul 04, 2025 at 09:54:28AM +, Michal Orzel wrote:
> When CONFIG_PDX_COMPRESSION=n, pdx_init_mask(), pdx_region_mask() and
> pfn_pdx_hole_setup() are just stubs doing nothing. It does not make
> sense to keep the two loops iterating over all the memory banks.
>
> Signed-of
Apologies for noise, my previous message was missing the intended tags:
On Fri, Jul 04, 2025 at 09:54:28AM +, Michal Orzel wrote:
> When CONFIG_PDX_COMPRESSION=n, pdx_init_mask(), pdx_region_mask() and
> pfn_pdx_hole_setup() are just stubs doing nothing. It does not make
> sense to keep the tw
On 05.07.2025 16:27, Koichiro Den wrote:
> --- a/xen/arch/arm/mm.c
> +++ b/xen/arch/arm/mm.c
> @@ -180,7 +180,21 @@ int xenmem_add_to_physmap_one(
> case XENMAPSPACE_dev_mmio:
> rc = map_dev_mmio_page(d, gfn, _mfn(idx));
> return rc;
> +case XENMAPSPACE_pv_time:
> +#ifdef
On 02/07/2025 16:13, Hari Limaye wrote:
> From: Luca Fancellu
>
> Implement a function to find the index of a MPU region in the xen_mpumap
> MPU region array. This function will be used in future commits to
> implement creating and destroying MPU regions.
>
> Signed-off-by: Luca Fancellu
> S
On 06.07.2025 17:57, Sergii Dmytruk wrote:
> On Wed, Jul 02, 2025 at 04:29:18PM +0200, Jan Beulich wrote:
>> Btw, a brief rev log would be nice here. I saw you have something in the
>> cover letter, but having to look in two places isn't very helpful.
>
> I don't really know how to effectively mai
On Fri, Jul 04, 2025 at 09:54:27AM +, Michal Orzel wrote:
> Harden the code by panicing if direct map is too small for current memory
NIT: s/panicing/panicking
> layout taking into account possible PDX compression. Otherwise the assert
> is observed:
> Assertion '(mfn_to_pdx(maddr_to_mfn(ma))
On 7/7/25 9:20 AM, Jan Beulich wrote:
On 04.07.2025 17:01, Oleksii Kurochko wrote:
On 7/1/25 3:49 PM, Jan Beulich wrote:
On 10.06.2025 15:05, Oleksii Kurochko wrote:
This patch introduces p2m_set_entry() and its core helper __p2m_set_entry() for
RISC-V, based loosely on the Arm implementation
On Mon, Jul 7, 2025 at 8:56 AM Jan Beulich wrote:
>
> Well, in the common case the original author would never change, and it would
> be their S-o-b that remains first forever. Anything else would need
> explaining.
So, I should swap the two S-o-b lines, gotcha.
P.
On 07.07.2025 16:44, Jan Beulich wrote:
> We're generally striving to minimize behavioral differences between PV
> and PVH Dom0. Using (just?) is_memory_hole() in the PVH case looks quite
> a bit weaker to me, compared to the page ownership check done in the PV
> case. Extend checking accordingly.
On 7/7/25 2:53 PM, Jan Beulich wrote:
On 07.07.2025 13:46, Oleksii Kurochko wrote:
On 7/7/25 9:20 AM, Jan Beulich wrote:
On 04.07.2025 17:01, Oleksii Kurochko wrote:
On 7/1/25 3:49 PM, Jan Beulich wrote:
On 10.06.2025 15:05, Oleksii Kurochko wrote:
This patch introduces p2m_set_entry() and
On 2025-07-06 23:31, Penny, Zheng wrote:
[Public]
-Original Message-
From: Jan Beulich
Sent: Friday, July 4, 2025 5:46 PM
To: Penny, Zheng
Cc: Huang, Ray ; Anthony PERARD
; Juergen Gross ; Andrew
Cooper ; Orzel, Michal ;
Julien Grall ; Roger Pau Monné ; Stefano
Stabellini ; xen-dev
On Mon, Jul 7, 2025 at 4:42 PM Jan Beulich wrote:
>
> On 07.07.2025 17:11, Frediano Ziglio wrote:
> > EFI code path split options from EFI LoadOptions fields in 2
> > pieces, first EFI options, second Xen options.
> > "get_argv" function is called first to get the number of arguments
> > in the Lo
On Mon, Jul 07, 2025 at 10:29:46AM +0200, Jan Beulich wrote:
> >> Btw, please don't forget to Cc maintainers of code you're changing /
> >> adding.
> >
> > What do you mean? I'm running add_maintainers.pl on the patches.
>
> The Cc: list had none of the REST maintainers. (Whether there's a bug in
Adds support for Meteor Lake C-states. As the spec is identical to Alder Lake
as per the Intel specs, I've reused the Alder Lake codepath.
Signed-off-by: Alex XZ Cypher Zero
---
xen/arch/x86/cpu/mwait-idle.c | 4
1 file changed, 4 insertions(+)
diff --git a/xen/arch/x86/cpu/mwait-idle.c b
Today, checking for non-fatal MCE errors on ARM is very invasive: it
involves a periodic timer interrupting the physical CPU execution at
regular intervals. Moreover, when the timer fires, the handler sends an
IPI to all physical CPUs.
Both these actions are disruptive in terms of latency and dete
On real time configuration with the null scheduler, we shouldn't
interrupt the guest execution unless strictly necessary: the guest could
be a real time guest (e.g. FreeRTOS) and interrupting its execution
could lead to a missed deadline.
The principal source of interruptions is IPIs. Remove the u
On Fri, 4 Jul 2025, Dmytro Prokopchuk1 wrote:
> Address a violation of MISRA C:2012 Rule 5.5:
> "Identifiers shall be distinct from macro names".
>
> Reports for service MC3A2.R5.5:
> xen/include/xen/fdt-domain-build.h: non-compliant parameter 'copy_to_guest'
> xen/include/xen/guest_access.h: non-
On Thu, Jul 03, 2025 at 12:25:27PM +0200, Jan Beulich wrote:
> On 30.05.2025 15:17, Sergii Dmytruk wrote:
> > From: Kacper Stojek
> >
> > Signed-off-by: Kacper Stojek
> > Signed-off-by: Krystian Hebel
> > Signed-off-by: Sergii Dmytruk
>
> Such a change can hardly come without any description. A
On Mon, 30 Jun 2025, Luca Fancellu wrote:
> Hi Michal,
>
> > On 25 Jun 2025, at 11:12, Michal Orzel wrote:
> >
> > At the moment, we unconditionally allocate space for grant table region
> > membank and add it in the membanks array to find_unallocated_memory() to
> > find unused memory. In case
On Fri, 20 Jun 2025, Jan Beulich wrote:
> On 19.06.2025 02:36, Stefano Stabellini wrote:
> > On Tue, 17 Jun 2025, Jan Beulich wrote:
> >> On 17.06.2025 02:10, Stefano Stabellini wrote:
> >>> On Mon, 16 Jun 2025, Jan Beulich wrote:
> On 14.06.2025 00:51, Stefano Stabellini wrote:
> > On Wed
On Tue, 24 Jun 2025, Jan Beulich wrote:
> On 24.06.2025 02:20, victorm.l...@amd.com wrote:
> > From: Nicola Vetrini
> >
> > Use {get,put}_unaligned_t to ensure that reads and writes are
> > safe to perform even on potentially misaligned pointers.
>
> Also applicable to the Arm patch: Please can
On Tue, 1 Jul 2025, Mykola Kvach wrote:
> From: Mykola Kvach
>
> Add a new entry under "Virtual Hardware, Hypervisor" for guest PSCI
> support on ARM. This documents support for all mandatory functions of
> PSCI 1.1, and separately lists the supported optional functions.
>
> Signed-off-by: Mykol
On 6/11/25 15:28, Stewart Hildebrand wrote:
> On 6/5/25 05:47, Roger Pau Monné wrote:
>> On Sat, May 31, 2025 at 08:53:59AM -0400, Stewart Hildebrand wrote:
>>> Since 622bdd962822 ("vpci/header: handle p2m range sets per BAR"), a
>>> non-const pdev is no longer needed for error handling in
>>> vpci
On Mon, 7 Jul 2025, Jan Beulich wrote:
> On 04.07.2025 22:39, Dmytro Prokopchuk1 wrote:
> > Address a violation of MISRA C:2012 Rule 5.5:
> > "Identifiers shall be distinct from macro names".
> >
> > Reports for service MC3A2.R5.5:
> > xen/include/xen/iommu.h: non-compliant struct 'page_list_head'
On Mon, 7 Jul 2025, Jan Beulich wrote:
> On 04.07.2025 22:39, Dmytro Prokopchuk1 wrote:
> > Address a violation of MISRA C:2012 Rule 5.5:
> > "Identifiers shall be distinct from macro names".
> >
> > Reports for service MC3A2.R5.5:
> > xen/include/xen/irq.h: non-compliant function `pirq_cleanup_ch
On Fri, 4 Jul 2025, Dmytro Prokopchuk1 wrote:
> Address a violation of MISRA C:2012 Rule 5.5:
> "Identifiers shall be distinct from macro names".
>
> Reports for service MC3A2.R5.5:
> xen/common/grant_table.c: non-compliant macro 'update_gnttab_par'
> xen/common/grant_table.c: non-compliant macro
On Fri, 4 Jul 2025, Dmytro Prokopchuk1 wrote:
> Address a violation of MISRA C:2012 Rule 5.5:
> "Identifiers shall be distinct from macro names".
>
> Reports for service MC3A2.R5.5:
> xen/include/xen/bitops.h: non-compliant function '__test_and_set_bit(int,
> volatile void*)'
> xen/include/xen/bi
On Fri, 4 Jul 2025, Jan Beulich wrote:
> On 04.07.2025 12:10, Sergiy Kibrik wrote:
> > 01.07.25 13:42, Jan Beulich:
> >> On 30.06.2025 10:55, Sergiy Kibrik wrote:
> >>> @@ -54,4 +54,7 @@ $(obj)/policy.bin: FORCE
> >>> FLASK_BUILD_DIR=$(FLASK_BUILD_DIR)
> >>> POLICY_FILENAME=$(POL
On Thu, 26 Jun 2025, Nicola Vetrini wrote:
> On 2025-06-24 08:11, Jan Beulich wrote:
> > On 24.06.2025 01:45, Stefano Stabellini wrote:
> > > Rule 21.16 is about the types of arguments allowed for memcpy.
> >
> > Seeing the subject - is it memcmp(), memcpy(), or both? (Writing from
> > home, where
Currently, the URL where the ECLAIR MISRA C scan reports are saved
is hardcoded; making it configurable allows multiple runners and storage
servers to be used without resorting to publishing all artifacts
to the same report server.
Additionally, reports will be accessed publicly by using a proxy,
On 07.07.2025 17:11, Frediano Ziglio wrote:
> EFI code path split options from EFI LoadOptions fields in 2
> pieces, first EFI options, second Xen options.
> "get_argv" function is called first to get the number of arguments
> in the LoadOptions, second, after allocating enough space, to
> fill som
Since 622bdd962822 ("vpci/header: handle p2m range sets per BAR"), a
non-const pdev is no longer needed for error handling in
vpci_process_pending(). Const-ify pdev in vpci_process_pending(),
defer_map(), and struct vpci_vcpu.
Get rid of const-removal workaround in modify_bars().
Take the opportu
On Mon, Jul 07, 2025 at 12:48:06PM +, Anthony PERARD wrote:
> On Mon, Jun 23, 2025 at 06:19:27PM -0700, Stefano Stabellini wrote:
> > diff --git a/xen/include/xen/compile.h.in b/xen/include/xen/compile.h.in
> > index 3151d1e7d1..9206341ba6 100644
> > --- a/xen/include/xen/compile.h.in
> > +++ b
On 7/7/25 5:15 PM, Jan Beulich wrote:
On 07.07.2025 17:00, Oleksii Kurochko wrote:
On 7/7/25 2:53 PM, Jan Beulich wrote:
On 07.07.2025 13:46, Oleksii Kurochko wrote:
On 7/7/25 9:20 AM, Jan Beulich wrote:
On 04.07.2025 17:01, Oleksii Kurochko wrote:
On 7/1/25 3:49 PM, Jan Beulich wrote:
On
EFI code path split options from EFI LoadOptions fields in 2
pieces, first EFI options, second Xen options.
"get_argv" function is called first to get the number of arguments
in the LoadOptions, second, after allocating enough space, to
fill some "argc"/"argv" variable. However the first parsing co
On 07.07.2025 17:00, Oleksii Kurochko wrote:
> On 7/7/25 2:53 PM, Jan Beulich wrote:
>> On 07.07.2025 13:46, Oleksii Kurochko wrote:
>>> On 7/7/25 9:20 AM, Jan Beulich wrote:
On 04.07.2025 17:01, Oleksii Kurochko wrote:
> On 7/1/25 3:49 PM, Jan Beulich wrote:
>> On 10.06.2025 15:05, Ol
On 07.07.2025 17:51, Frediano Ziglio wrote:
> On Mon, Jul 7, 2025 at 4:42 PM Jan Beulich wrote:
>>
>> On 07.07.2025 17:11, Frediano Ziglio wrote:
>>> EFI code path split options from EFI LoadOptions fields in 2
>>> pieces, first EFI options, second Xen options.
>>> "get_argv" function is called fi
On Fri, 4 Jul 2025, Michal Orzel wrote:
> The current look and feel of setup_mm() leaves a lot to be desired. The
> scope of variables is not the best, many variables are not really needed
> while some others are set but not used. The first iteration of membanks
> is split from the loop for no reas
On Fri, 4 Jul 2025, Michal Orzel wrote:
> Harden the code by panicing if direct map is too small for current memory
> layout taking into account possible PDX compression. Otherwise the assert
> is observed:
> Assertion '(mfn_to_pdx(maddr_to_mfn(ma)) - directmap_base_pdx) <
> (DIRECTMAP_SIZE >> PAG
On Fri, 4 Jul 2025, Michal Orzel wrote:
> When CONFIG_PDX_COMPRESSION=n, pdx_init_mask(), pdx_region_mask() and
> pfn_pdx_hole_setup() are just stubs doing nothing. It does not make
> sense to keep the two loops iterating over all the memory banks.
>
> Signed-off-by: Michal Orzel
Reviewed-by: St
Hi Michal,
> On Fri, Jul 04, 2025 at 11:08:31AM +, Michal Orzel wrote:
> The current look and feel of setup_mm() leaves a lot to be desired. The
> scope of variables is not the best, many variables are not really needed
> while some others are set but not used. The first iteration of membanks
Hi Julien,
> On 30/06/2025 13:44, Julien Grall wrote:
>> On 25/06/2025 16:53, Julien Grall wrote:
>
>> Hi Jahan,
>
>> +dsb(sy);
> Any clue why Linux (mainline) does not do that?
> I understand for the PCI passthrough, Xen will be using stage-2, so in theory
> the stage-1 could be u
Hi Jahan,
On 07/07/2025 12:24, Jahan Murudi wrote:
On 30/06/2025 13:44, Julien Grall wrote:
On 25/06/2025 16:53, Julien Grall wrote:
Hi Jahan,
+dsb(sy);
Any clue why Linux (mainline) does not do that?
I understand for the PCI passthrough, Xen will be using stage-2, so in theory
There is no need to use a populated memory page for mapping the shared
info page at that location. Just use an allocated virtual address for
the shared info page. For PVH allocate an unused pfn.
Signed-off-by: Juergen Gross
---
arch/x86/mm.c | 7 ---
arch/x86/setup.c | 15 -
Add a small pool of statically allocated memory pages to be handed out
for very early page table allocations.
This will make it possible to do virtual allocations e.g. for mapping
the shared info page.
Signed-off-by: Juergen Gross
---
arch/x86/mm.c | 16 +++-
1 file changed, 15 inse
Hi all,
This short patch series improves Xen real-time execution on AMD x86
processors.
The key to real-time performance is deterministic guest execution times
and deterministic guest interrupt latency. In such configurations, the
null scheduler is typically used, and there should be no IPIs or o
On 7/4/25 06:48, Jan Beulich wrote:
On 04.07.2025 12:10, Sergiy Kibrik wrote:
01.07.25 13:42, Jan Beulich:
On 30.06.2025 10:55, Sergiy Kibrik wrote:
@@ -54,4 +54,7 @@ $(obj)/policy.bin: FORCE
FLASK_BUILD_DIR=$(FLASK_BUILD_DIR) POLICY_FILENAME=$(POLICY_SRC)
cmp -s $(POLI
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