On 2019/1/29 19:11, Jan Beulich wrote:
Pu Wen 12/20/18 2:16 PM >>>
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -1973,6 +1973,8 @@ static unsigned int calc_ler_msr(void)
return MSR_IA32_LASTINTFROMIP;
}
break;
+case X86_VENDOR_HYGON:
+return MSR_IA32_LASTINTFROMIP;
Wit
>>> Pu Wen 12/20/18 2:16 PM >>>
>--- a/xen/arch/x86/traps.c
>+++ b/xen/arch/x86/traps.c
>@@ -1973,6 +1973,8 @@ static unsigned int calc_ler_msr(void)
>return MSR_IA32_LASTINTFROMIP;
>}
>break;
>+case X86_VENDOR_HYGON:
>+return MSR_IA32_LASTINTFROMIP;
With a blank line added above your
The Hygon Dhyana processor has the methold to get the last exception
source IP from MSR_01DD. So add support for it if the boot param
ler is true.
Signed-off-by: Pu Wen
---
xen/arch/x86/traps.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
