Re: [PATCH v3 3/5] x86/mwait-idle: add AlderLake support

2022-10-13 Thread Roger Pau Monné
On Thu, Aug 18, 2022 at 03:04:28PM +0200, Jan Beulich wrote: > From: Zhang Rui > > Similar to SPR, the C1 and C1E states on ADL are mutually exclusive. > Only one of them can be enabled at a time. > > But contrast to SPR, which usually has a strong latency requirement > as a Xeon processor, C1E

[PATCH v3 3/5] x86/mwait-idle: add AlderLake support

2022-08-18 Thread Jan Beulich
From: Zhang Rui Similar to SPR, the C1 and C1E states on ADL are mutually exclusive. Only one of them can be enabled at a time. But contrast to SPR, which usually has a strong latency requirement as a Xeon processor, C1E is preferred on ADL for better energy efficiency. Add custom C-state table