On Thu, Aug 18, 2022 at 03:04:28PM +0200, Jan Beulich wrote: > From: Zhang Rui <rui.zh...@intel.com> > > Similar to SPR, the C1 and C1E states on ADL are mutually exclusive. > Only one of them can be enabled at a time. > > But contrast to SPR, which usually has a strong latency requirement > as a Xeon processor, C1E is preferred on ADL for better energy > efficiency. > > Add custom C-state tables for ADL with both C1 and C1E, and > > 1. Enable the "C1E promotion" bit in MSR_IA32_POWER_CTL and mark C1 > with the CPUIDLE_FLAG_UNUSABLE flag, so C1 is not available by > default. > > 2. Add support for the "preferred_cstates" module parameter, so that > users can choose to use C1 instead of C1E by booting with > "intel_idle.preferred_cstates=2". > > Separate custom C-state tables are introduced for the ADL mobile and > desktop processors, because of the exit latency differences between > these two variants, especially with respect to PC10. > > Signed-off-by: Zhang Rui <rui.zh...@intel.com> > [ rjw: Changelog edits, code rearrangement ] > Signed-off-by: Rafael J. Wysocki <rafael.j.wyso...@intel.com> > Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git > d1cf8bbfed1e > Signed-off-by: Jan Beulich <jbeul...@suse.com>
Acked-by: Roger Pau Monné <roger....@citrix.com> Thanks, Roger.
