On 16/03/2025 20:24, Luca Fancellu wrote:
>
>
> From: Penny Zheng
>
> ARM MPU system doesn't need to use paging memory pool, as MPU memory
> mapping table at most takes only one 4KB page, which is enough to
> manage the maximum 255 MPU memory regions, for all EL2 stage 1
> translation and EL
On 17.03.2025 10:29, Luca Fancellu wrote:
>> On 17 Mar 2025, at 08:41, Jan Beulich wrote:
>> On 16.03.2025 20:24, Luca Fancellu wrote:
>>> --- a/xen/common/Kconfig
>>> +++ b/xen/common/Kconfig
>>> @@ -74,6 +74,9 @@ config HAS_KEXEC
>>> config HAS_LLC_COLORING
>>> bool
>>>
>>> +config HAS_PAGING_ME
Hi Jan,
> On 17 Mar 2025, at 08:41, Jan Beulich wrote:
>
> On 16.03.2025 20:24, Luca Fancellu wrote:
>> --- a/xen/common/Kconfig
>> +++ b/xen/common/Kconfig
>> @@ -74,6 +74,9 @@ config HAS_KEXEC
>> config HAS_LLC_COLORING
>> bool
>>
>> +config HAS_PAGING_MEMPOOL
>> + bool
>
> Imo this is too l
On 16.03.2025 20:24, Luca Fancellu wrote:
> --- a/xen/common/Kconfig
> +++ b/xen/common/Kconfig
> @@ -74,6 +74,9 @@ config HAS_KEXEC
> config HAS_LLC_COLORING
> bool
>
> +config HAS_PAGING_MEMPOOL
> + bool
Imo this is too little of a change outside of Arm-specific code here. Just
go g
From: Penny Zheng
ARM MPU system doesn't need to use paging memory pool, as MPU memory
mapping table at most takes only one 4KB page, which is enough to
manage the maximum 255 MPU memory regions, for all EL2 stage 1
translation and EL1 stage 2 translation.
Introduce HAS_PAGING_MEMPOOL Kconfig co
