alization/teardown of altp2m views.
Signed-off-by: Sergej Proskurin
---
Cc: Stefano Stabellini
Cc: Julien Grall
---
v2: Added the function p2m_flush_table to the previous version.
v3: Removed struct vttbr.
Moved define INVALID_VTTBR to p2m.h.
Exported function prototypes of "p2m_flus
lled/invalid entries.
Signed-off-by: Sergej Proskurin
---
Cc: Stefano Stabellini
Cc: Julien Grall
---
v3: Cosmetic fixes.
Changed the locking mechanism to "p2m_write_lock" inside the
function "altp2m_reset".
Removed TLB flushing and resetting of the max_mapped_gfn
The function "p2m_alloc_table" should be able to allocate 2nd stage
translation tables not only for the host's p2m but also for alternate
p2m's.
Signed-off-by: Sergej Proskurin
Acked-by: Julien Grall
---
Cc: Stefano Stabellini
Cc: Julien Grall
---
v2: Removed altp2m table
violations will trap into Xen and be forced by xen-access
to switch to the default view (altp2m[0]) as before. The introduced test
can be invoked by providing the argument "altp2m_remap".
Signed-off-by: Sergej Proskurin
---
Cc: Razvan Cojocaru
Cc: Tamas K Lengyel
Cc: Ian Jackson
Signed-off-by: Sergej Proskurin
---
Cc: Stefano Stabellini
Cc: Julien Grall
---
xen/include/asm-arm/altp2m.h | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/xen/include/asm-arm/altp2m.h b/xen/include/asm-arm/altp2m.h
index f9e14ab1dc..eff6bd5a38 100644
--- a/xen/include
We move the macros (MAX|INVALID)_ALTP2M out of x86-related code to
common code, as the following patches will make use of them on ARM.
Signed-off-by: Sergej Proskurin
---
Cc: Andrew Cooper
Cc: George Dunlap
Cc: Ian Jackson
Cc: Jan Beulich
Cc: Konrad Rzeszutek Wilk
Cc: Stefano Stabellini
Cc
This commit adopts the x86 HVMOP_altp2m_get_domain_state implementation.
Signed-off-by: Sergej Proskurin
---
Cc: Stefano Stabellini
Cc: Julien Grall
---
v3: Removed the "altp2m_enabled" check in HVMOP_altp2m_get_domain_state
case as it has been moved in front of the switch st
currently
active altp2m view might not have the required gva mapping yet.
Also, the new implementation fills the request buffer to hold
altp2m-related information.
Signed-off-by: Sergej Proskurin
---
Cc: Stefano Stabellini
Cc: Julien Grall
---
v3: Extended the function "p2m_mem_access_ch
Hi Razvan,
On 08/30/2017 08:42 PM, Razvan Cojocaru wrote:
> On 08/30/2017 09:32 PM, Sergej Proskurin wrote:
>> diff --git a/xen/common/vm_event.c b/xen/common/vm_event.c
>> index 42e6f09029..66f1d83d84 100644
>> --- a/xen/common/vm_event.c
>> +++ b/xen/common/v
Hi Razvan,
[...]
>> +
>> +*gfn_new = ++(xenaccess->max_gpfn);
> Unnecessary parentheses.
>
Thanks.
>> +rc = xc_domain_populate_physmap_exact(xenaccess->xc_handle, domain_id,
>> 1, 0, 0, gfn_new);
>> +if ( rc < 0 )
>> +goto err;
>> +
>> +/* Copy content of the old gfn i
Hi Jan,
On 08/31/2017 10:04 AM, Jan Beulich wrote:
On 30.08.17 at 20:32, wrote:
>> We move the macros (MAX|INVALID)_ALTP2M out of x86-related code to
>> common code, as the following patches will make use of them on ARM.
> But both seem not impossible to be require arch-specific values.
Ri
Hi Volodymyr, hi Julien,
On 08/24/2017 07:25 PM, Julien Grall wrote:
>
>
> On 21/08/17 21:27, Volodymyr Babchuk wrote:
>> This feature indicates that hypervisor is compatible with ARM
>> SMC calling convention. Hypervisor will not inject an undefined
>> instruction exception if an invalid SMC fun
Hi Volodymyr,
On 08/31/2017 02:44 PM, Volodymyr Babchuk wrote:
> Hello Sergej,
>
> On 31.08.17 15:20, Sergej Proskurin wrote:
>> Hi Volodymyr, hi Julien,
>>
>>
>> On 08/24/2017 07:25 PM, Julien Grall wrote:
>>>
>>>
>>> On 21/08/17 21:2
Hi Jan,
On 08/31/2017 12:19 PM, Jan Beulich wrote:
On 31.08.17 at 11:49, wrote:
>> On 08/31/2017 10:04 AM, Jan Beulich wrote:
>> On 30.08.17 at 20:32, wrote:
We move the macros (MAX|INVALID)_ALTP2M out of x86-related code to
common code, as the following patches will make use
Hi Volodymyr,
On 08/31/2017 04:58 PM, Volodymyr Babchuk wrote:
> Hi Sergej
>
> On 31.08.17 16:51, Sergej Proskurin wrote:
>> Hi Volodymyr,
>>
>>
>> On 08/31/2017 02:44 PM, Volodymyr Babchuk wrote:
>>> Hello Sergej,
>>>
>>> On 31.08.17
Hi Julien,
On 09/04/2017 08:07 AM, Julien Grall wrote:
> Hello,
>
> Sorry for the formatting, writing from my phone. Ki
>
> On Thu, 31 Aug 2017, 22:18 Sergej Proskurin wrote:
>
[...]
>
> On your first mail, you started with "smc injection doesn't work",
In this commit, we extend the capabilities of the monitor to allow
tracing of single-step events on ARM.
Signed-off-by: Sergej Proskurin
---
Cc: Razvan Cojocaru
Cc: Tamas K Lengyel
Cc: Stefano Stabellini
Cc: Julien Grall
---
xen/arch/arm/monitor.c| 23 +++
xen
This commit adds the domctl that is required to enable single-stepping
on ARM.
Signed-off-by: Sergej Proskurin
---
Cc: Stefano Stabellini
Cc: Julien Grall
---
xen/arch/arm/domctl.c| 35 +++
xen/include/asm-arm/domain.h | 2 ++
2 files changed, 37
This commit concludes the single-stepping functionality on ARM by adding
trapping on and setting up single-stepping events of the architecture.
Signed-off-by: Sergej Proskurin
---
Cc: Stefano Stabellini
Cc: Julien Grall
---
xen/arch/arm/arm64/entry.S | 2 ++
xen/arch/arm/traps.c
In this commit we move the declaration of the function
vm_event_toggle_singlestep from to and
implement the associated functionality on ARM.
Signed-off-by: Sergej Proskurin
---
Cc: Razvan Cojocaru
Cc: Tamas K Lengyel
Cc: Stefano Stabellini
Cc: Julien Grall
Cc: Jan Beulich
Cc: Andrew
r use case.
It would be of great help if we would discuss the upper issue and
hopefully even find a solution to the presented issue.
Thank you very much in advance.
Cheers,
~Sergej
[0] https://lists.xen.org/archives/html/xen-devel/2017-08/msg00661.html
Sergej Proskurin (4):
arm/monitor: Introduc
let me know if I
should wait for reviews until the end of the extended code freeze deadline.
Thanks,
~Sergej
On 08/30/2017 08:32 PM, Sergej Proskurin wrote:
> Hi all,
>
> The following patch series can be found on Github[0] and is part of my
> contribution to last year's Goog
Hi Julien,
On 10/07/2017 12:29 PM, Julien Grall wrote:
>
>
> On 07/10/2017 11:18, Sergej Proskurin wrote:
>> Hi all,
>
> Hello Sergej,
>
>>
>> just wanted to friendly remind you about the next altp2m on ARM patch
>> series, since it has been submitte
oduced software page-table walk for stage-1.
>
> Coverity-ID: 1457707
> Signed-off-by: Julien Grall
>
> ---
>
> Cc: Sergej Proskurin
Acked-by: Sergej Proskurin
Thanks,
~Sergej
> ---
> xen/arch/arm/guest_walk.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(
iew comments to the
initial implementation. You did not want to see any #define
CONFIG_ARM_64 within the code. TCR_EL1 is a 64-bit Register: to prevent
compilation issues for Aarch32 systems, why don't you use uint64_t for
ips instead of register_t?
Thanks,
~Sergej
>
> Coverity-ID: 14577
Hi Julien,
On 10/11/2017 04:57 PM, Julien Grall wrote:
>
>
> On 11/10/17 15:51, Sergej Proskurin wrote:
>> Hi Julien,
>
> Hi,
>
>> On 10/11/2017 04:29 PM, Julien Grall wrote:
>>> The function get_ipa_output_size is check whether the input size
>&g
Hi Julien,
On 07/17/2017 05:43 PM, Julien Grall wrote:
> Hi Sergej,
>
> On 06/07/17 12:50, Sergej Proskurin wrote:
>> This commit renames the function vgic_access_guest_memory to
>> access_guest_memory_by_ipa. As the function name suggests, the functions
>> expects a
Hi Julien,
On 07/17/2017 05:38 PM, Julien Grall wrote:
> Hi Sergej,
>
> On 06/07/17 12:50, Sergej Proskurin wrote:
>> This commit moves the function vgic_access_guest_memory to guestcopy.c
>> and the header asm/guest_access.h. No functional changes are made.
>> Please
will be
submitted in the future.
Signed-off-by: Sergej Proskurin
Acked-by: Julien Grall
---
Cc: Razvan Cojocaru
Cc: Tamas K Lengyel
Cc: Stefano Stabellini
Cc: Julien Grall
---
v1:
This commit has been already acknowledged in the altp2m patch
series, however not yet applied to mainline.
Hi Julien,
On 07/18/2017 12:43 PM, Julien Grall wrote:
>
>
> On 18/07/17 10:49, Sergej Proskurin wrote:
>> Hi Julien,
>
> Hello Sergej,
>
>>
>> On 07/17/2017 05:38 PM, Julien Grall wrote:
>>> Hi Sergej,
>>>
>>> On 06/07/17 12:
On 07/18/2017 02:12 PM, Julien Grall wrote:
>
>
> On 18/07/17 12:59, Sergej Proskurin wrote:
>> Hi Julien,
>>
>>
>> On 07/18/2017 12:43 PM, Julien Grall wrote:
>>>
>>>
>>> On 18/07/17 10:49, Sergej Proskurin wrote:
>>>> Hi Ju
AArch64 supports pages with different (4K, 16K, and 64K) sizes. To
enable guest page table walks for various configurations, this commit
extends the defines and helpers of the current implementation.
Signed-off-by: Sergej Proskurin
Reviewed-by: Julien Grall
---
Cc: Stefano Stabellini
Cc
commits.
Signed-off-by: Sergej Proskurin
Reviewed-by: Julien Grall
---
Cc: Stefano Stabellini
Cc: Julien Grall
---
v4: We reused the previous commit with the msg "arm/mem_access: Add
defines holding the width of 32/64bit regs" from v3, as we can reuse
the already exist
We extend the current implementation by an additional permission,
GV2M_EXEC, which will be used to describe execute permissions of PTE's
as part of our guest translation table walk implementation.
Signed-off-by: Sergej Proskurin
Acked-by: Julien Grall
---
Cc: Stefano Stabellini
Cc: J
The current implementation does not provide appropriate types for
short-descriptor translation table entries. As such, this commit adds new
types, which simplify managing the respective translation table entries.
Signed-off-by: Sergej Proskurin
Acked-by: Julien Grall
---
Cc: Stefano Stabellini
This commit adds (TCR_|TTBCR_)* defines to simplify access to the
respective register contents. At the same time, we adjust the macros
TCR_T0SZ and TCR_TG0_* by using the newly introduced TCR_T0SZ_SHIFT and
TCR_TG0_SHIFT instead of the hardcoded values.
Signed-off-by: Sergej Proskurin
Acked-by
-step potential translation errors in the function
p2m_mem_access_check_and_get_page due to restricted memory (e.g. to the
guest's page tables themselves), we walk the guest's page tables in
software.
Signed-off-by: Sergej Proskurin
Acked-by: Tamas K Lengyel
---
Cc: Razvan Cojocaru
Cc: Tama
xen/page-defs.h as
to allow the following commits to use the consolidated defines.
Signed-off-by: Sergej Proskurin
---
Cc: Andrew Cooper
Cc: George Dunlap
Cc: Ian Jackson
Cc: Jan Beulich
Cc: Julien Grall
Cc: Konrad Rzeszutek Wilk
Cc: Stefano Stabellini
Cc: Tim Deegan
Cc: Wei Liu
---
v6
eliminate artefacts of the function's
previous location.
Signed-off-by: Sergej Proskurin
---
Cc: Stefano Stabellini
Cc: Julien Grall
---
v6: We added this patch to our patch series.
v7: Renamed the function's argument ipa back to gpa.
Removed any mentioning of "vITS&quo
This commit moves the function vgic_access_guest_memory to guestcopy.c
and the header asm/guest_access.h. No functional changes are made.
Please note that the function will be renamed in the following commit.
Signed-off-by: Sergej Proskurin
Acked-by: Julien Grall
---
Cc: Stefano Stabellini
Cc
ng of macros and
function parameters. Some additional changes comprising code readability and
correct type usage have been made and stated in the individual commits.
The following patch series can be found on Github[0].
Cheers,
~Sergej
[0] https://github.com/sergej-proskurin/xen (branch arm-gpt-wa
This commit introduces a new helper that checks whether the target PTE
holds a page mapping or not. This helper will be used as part of the
following commits.
Signed-off-by: Sergej Proskurin
Reviewed-by: Julien Grall
---
Cc: Stefano Stabellini
Cc: Julien Grall
---
v6: Change the name of the
implementation has been lifted from the linux kernel source
code.
Signed-off-by: Sergej Proskurin
---
Cc: Andrew Cooper
Cc: George Dunlap
Cc: Ian Jackson
Cc: Jan Beulich
Cc: Julien Grall
Cc: Konrad Rzeszutek Wilk
Cc: Stefano Stabellini
Cc: Tim Deegan
Cc: Wei Liu
---
v6: As similar patches have been
TTBR0_EL1, TTBR1_EL1, and
SCTLR_EL1.
Signed-off-by: Sergej Proskurin
Acked-by: Julien Grall
---
Cc: Stefano Stabellini
Cc: Julien Grall
---
v2: Rename p2m_gva_to_ipa to p2m_walk_gpt and move it to p2m.c.
Move the functionality responsible for walking long-descriptor based
translation tab
M DDI 0487B.a J1-5922, J1-5999, and ARM DDI 0406C.b B3-1510.
Note that the current implementation lacks support for Large VA/PA on
ARMv8.2 architectures (LVA/LPA, 52-bit virtual and physical address
sizes). The associated location in the code is marked appropriately.
Signed-off-by: Sergej Proskurin
-
This commit adds functionality to walk the guest's page tables using the
short-descriptor translation table format for both ARMv7 and ARMv8. The
implementation is based on ARM DDI 0487B-a J1-6002 and ARM DDI 0406C-b
B3-1506.
Signed-off-by: Sergej Proskurin
Acked-by: Julien Grall
---
Cc: St
Hi Wei,
On 07/18/2017 01:16 PM, Wei Liu wrote:
> On Mon, Jul 17, 2017 at 06:19:09PM +0200, Sergej Proskurin wrote:
>> Hi Julien,
>>
>>
>> On 07/17/2017 03:53 PM, Julien Grall wrote:
>>> (+Wei and Ian)
>>>
>>> Hi Sergej
>>>
>>&
Hi Wei,
On 07/19/2017 12:22 PM, Wei Liu wrote:
> On Wed, Jul 19, 2017 at 11:40:19AM +0200, Sergej Proskurin wrote:
>> Hi Wei,
>>
>>
>> On 07/18/2017 01:16 PM, Wei Liu wrote:
>>> On Mon, Jul 17, 2017 at 06:19:09PM +0200, Sergej Proskurin wrote:
>>>&g
On 07/19/2017 01:57 PM, Wei Liu wrote:
> On Wed, Jul 19, 2017 at 01:52:08PM +0200, Sergej Proskurin wrote:
>> ---
>> root@avocet:~# xl list
>> NameID Mem VCPUs State
>> Time(s)
>> Domain-0
Hi Julien,
Sorry for the late reply.
On 07/31/2017 04:38 PM, Julien Grall wrote:
>
>
> On 18/07/17 13:24, Sergej Proskurin wrote:
>> Hi all,
>
> Hi,
>
>>
>> The function p2m_mem_access_check_and_get_page is called from the function
>> get_pag
Hi Julien,
On 08/04/2017 11:15 AM, Sergej Proskurin wrote:
> Hi Julien,
>
> Sorry for the late reply.
>
> On 07/31/2017 04:38 PM, Julien Grall wrote:
>>
>> On 18/07/17 13:24, Sergej Proskurin wrote:
>>> Hi all,
>> Hi,
>>
>>> The func
Hi Julien,
> The patch belows solve my problem:
>
> diff --git a/xen/arch/arm/guest_walk.c b/xen/arch/arm/guest_walk.c
> index b258248322..6ca994e438 100644
> --- a/xen/arch/arm/guest_walk.c
> +++ b/xen/arch/arm/guest_walk.c
> @@ -112,7 +112,7 @@ static int guest_walk_sd(const struct vcpu *v,
>
On 08/08/2017 04:58 PM, Andrew Cooper wrote:
> On 08/08/17 15:47, Sergej Proskurin wrote:
>> Hi Julien,
>>
>>> The patch belows solve my problem:
>>>
>>> diff --git a/xen/arch/arm/guest_walk.c b/xen/arch/arm/guest_walk.c
>>> index b258248322..6c
Hi Julien,
On 07/18/2017 02:25 PM, Sergej Proskurin wrote:
> This commit adds functionality to walk the guest's page tables using the
> short-descriptor translation table format for both ARMv7 and ARMv8. The
> implementation is based on ARM DDI 0487B-a J1-6002 and ARM DDI 040
On 08/08/2017 05:18 PM, Julien Grall wrote:
>
>
> On 08/08/17 16:17, Sergej Proskurin wrote:
>> Hi Julien,
>>
>>
>> On 07/18/2017 02:25 PM, Sergej Proskurin wrote:
>>> This commit adds functionality to walk the guest's page tables using
>>&g
On 08/08/2017 06:20 PM, Andrew Cooper wrote:
> On 08/08/17 16:28, Sergej Proskurin wrote:
>> On 08/08/2017 05:18 PM, Julien Grall wrote:
>>> On 08/08/17 16:17, Sergej Proskurin wrote:
>>>> Hi Julien,
>>>>
>>>>
>>>> On 0
Hi Andrew,
>>> diff --git a/xen/arch/arm/guest_walk.c b/xen/arch/arm/guest_walk.c
>>> index b258248322..7f34a2b1d3 100644
>>> --- a/xen/arch/arm/guest_walk.c
>>> +++ b/xen/arch/arm/guest_walk.c
>>> @@ -112,7 +112,12 @@ static int guest_walk_sd(const struct vcpu *v,
>>> * level translati
This commit introduces a new helper that checks whether the target PTE
holds a page mapping or not. This helper will be used as part of the
following commits.
Signed-off-by: Sergej Proskurin
Reviewed-by: Julien Grall
---
Cc: Stefano Stabellini
Cc: Julien Grall
---
v6: Change the name of the
This commit moves the function vgic_access_guest_memory to guestcopy.c
and the header asm/guest_access.h. No functional changes are made.
Please note that the function will be renamed in the following commit.
Signed-off-by: Sergej Proskurin
Acked-by: Julien Grall
---
Cc: Stefano Stabellini
Cc
This commit adds (TCR_|TTBCR_)* defines to simplify access to the
respective register contents. At the same time, we adjust the macros
TCR_T0SZ and TCR_TG0_* by using the newly introduced TCR_T0SZ_SHIFT and
TCR_TG0_SHIFT instead of the hardcoded values.
Signed-off-by: Sergej Proskurin
Acked-by
eliminate artefacts of the function's
previous location.
Signed-off-by: Sergej Proskurin
---
Cc: Stefano Stabellini
Cc: Julien Grall
---
v6: We added this patch to our patch series.
v7: Renamed the function's argument ipa back to gpa.
Removed any mentioning of "vITS&quo
AArch64 supports pages with different (4K, 16K, and 64K) sizes. To
enable guest page table walks for various configurations, this commit
extends the defines and helpers of the current implementation.
Signed-off-by: Sergej Proskurin
Reviewed-by: Julien Grall
---
Cc: Stefano Stabellini
Cc
The current implementation does not provide appropriate types for
short-descriptor translation table entries. As such, this commit adds new
types, which simplify managing the respective translation table entries.
Signed-off-by: Sergej Proskurin
Acked-by: Julien Grall
---
Cc: Stefano Stabellini
t and
position where we recursively rely on the p2m->lock. We also add casts
to fields of the struct short_desc_t in guest_walk_sd as to cope with
incorrect values due to the C type promotion.
The following patch series can be found on Github[0].
Cheers,
~Sergej
[0] https://github.com/sergej-prosk
implementation has been lifted from the linux kernel source
code.
Signed-off-by: Sergej Proskurin
---
Cc: Andrew Cooper
Cc: George Dunlap
Cc: Ian Jackson
Cc: Jan Beulich
Cc: Julien Grall
Cc: Konrad Rzeszutek Wilk
Cc: Stefano Stabellini
Cc: Tim Deegan
Cc: Wei Liu
---
v6: As similar patches have been
TTBR0_EL1, TTBR1_EL1, and
SCTLR_EL1.
Signed-off-by: Sergej Proskurin
Acked-by: Julien Grall
---
Cc: Stefano Stabellini
Cc: Julien Grall
---
v2: Rename p2m_gva_to_ipa to p2m_walk_gpt and move it to p2m.c.
Move the functionality responsible for walking long-descriptor based
translation tab
-step potential translation errors in the function
p2m_mem_access_check_and_get_page due to restricted memory (e.g. to the
guest's page tables themselves), we walk the guest's page tables in
software.
Signed-off-by: Sergej Proskurin
Acked-by: Tamas K Lengyel
---
Cc: Razvan Cojocaru
Cc: Tama
We extend the current implementation by an additional permission,
GV2M_EXEC, which will be used to describe execute permissions of PTE's
as part of our guest translation table walk implementation.
Signed-off-by: Sergej Proskurin
Acked-by: Julien Grall
---
Cc: Stefano Stabellini
Cc: J
commits.
Signed-off-by: Sergej Proskurin
Reviewed-by: Julien Grall
---
Cc: Stefano Stabellini
Cc: Julien Grall
---
v4: We reused the previous commit with the msg "arm/mem_access: Add
defines holding the width of 32/64bit regs" from v3, as we can reuse
the already exist
This commit adds functionality to walk the guest's page tables using the
short-descriptor translation table format for both ARMv7 and ARMv8. The
implementation is based on ARM DDI 0487B-a J1-6002 and ARM DDI 0406C-b
B3-1506.
Signed-off-by: Sergej Proskurin
Acked-by: Julien Grall
---
Cc: St
M DDI 0487B.a J1-5922, J1-5999, and ARM DDI 0406C.b B3-1510.
Note that the current implementation lacks support for Large VA/PA on
ARMv8.2 architectures (LVA/LPA, 52-bit virtual and physical address
sizes). The associated location in the code is marked appropriately.
Signed-off-by: Sergej Proskurin
-
Hi Julien,
On 08/14/2017 07:37 PM, Julien Grall wrote:
> Hi Sergej,
>
> On 09/08/17 09:20, Sergej Proskurin wrote:
>> +/*
>> + * According to to ARM DDI 0487B.a J1-5927, we return an error if
>> the found
>
> Please drop one of the 'to'. The
Hi Julien,
[...]
On 06/19/2017 02:45 PM, Julien Grall wrote:
> Hi Sergej,
>
>> +/* Normalized page granule size indices. */
>> +#define GRANULE_SIZE_INDEX_4K (0)
>> +#define GRANULE_SIZE_INDEX_16K (1)
>> +#define GRANULE_SIZE_INDEX_64K (2)
>
> Why this is e
This commit adds (TCR_|TTBCR_)* defines to simplify access to the
respective register contents. At the same time, we adjust the macro
TCR_T0SZ by using the newly introduced TCR_T0SZ_SHIFT instead of the
hardcoded value.
Signed-off-by: Sergej Proskurin
---
Cc: Stefano Stabellini
Cc: Julien Grall
The current implementation does not provide appropriate types for
short-descriptor translation table entries. As such, this commit adds new
types, which simplify managing the respective translation table entries.
Signed-off-by: Sergej Proskurin
---
Cc: Stefano Stabellini
Cc: Julien Grall
This commit adds functionality to walk the guest's page tables using the
short-descriptor translation table format for both ARMv7 and ARMv8. The
implementation is based on ARM DDI 0487B-a J1-6002 and ARM DDI 0406C-b
B3-1506.
Signed-off-by: Sergej Proskurin
---
Cc: Stefano Stabellini
Cc: J
TTBR0_EL1, TTBR1_EL1, and
SCTLR_EL1.
Signed-off-by: Sergej Proskurin
---
Cc: Stefano Stabellini
Cc: Julien Grall
---
v2: Rename p2m_gva_to_ipa to p2m_walk_gpt and move it to p2m.c.
Move the functionality responsible for walking long-descriptor based
translation tables out of the function p2
We extend the current implementation by an additional permission,
GV2M_EXEC, which will be used to describe execute permissions of PTE's
as part of our guest translation table walk implementation.
Signed-off-by: Sergej Proskurin
Acked-by: Julien Grall
---
Cc: Stefano Stabellini
Cc: J
.
Signed-off-by: Sergej Proskurin
---
Cc: Stefano Stabellini
Cc: Julien Grall
---
v4: We reused the previous commit with the msg "arm/mem_access: Add
defines holding the width of 32/64bit regs" from v3, as we can reuse
the already existing define BITS_PER_WORD.
---
xen/inclu
-step potential translation errors in the function
p2m_mem_access_check_and_get_page due to restricted memory (e.g. to the
guest's page tables themselves), we walk the guest's page tables in
software.
Signed-off-by: Sergej Proskurin
---
Cc: Razvan Cojocaru
Cc: Tamas K Lengyel
Cc: Stefano
M DDI 0487B.a J1-5922, J1-5999, and ARM DDI 0406C.b B3-1510.
Note that the current implementation lacks support for Large VA/PA on
ARMv8.2 architectures (LVA/LPA, 52-bit virtual and physical address
sizes). The associated location in the code is marked appropriately.
Signed-off-by: Sergej Proskurin
-
The ARMv8 architecture supports pages with different (4K, 16K, and 64K) sizes.
To enable guest page table walks for various configurations, this commit
extends the defines and helpers of the current implementation.
Signed-off-by: Sergej Proskurin
---
Cc: Stefano Stabellini
Cc: Julien Grall
arate header"[1].
The following patch series can be found on Github[0].
Cheers,
~Sergej
[0] https://github.com/sergej-proskurin/xen (branch arm-gpt-walk-v4)
[1] https://lists.xen.org/archives/html/xen-devel/2017-06/msg02095.html
Sergej Proskurin (9):
arm/mem_access: Add (TCR_|TTBCR_)* defi
Hi Tamas,
[...]
>> +if ( guest_walk_tables(v, gva, &ipa, &perms) < 0 )
>> +/*
>> + * The software gva to ipa translation can still fail, e.g., if
>> the
>> + * gva is not mapped.
>> + */
>
> If you end up sending another round of the serie
Hi Julien,
On 06/22/2017 01:16 PM, Julien Grall wrote:
> Hi Sergej,
>
> On 20/06/17 21:33, Sergej Proskurin wrote:
>> +int guest_walk_tables(const struct vcpu *v, vaddr_t gva,
>> + paddr_t *ipa, unsigned int *perms)
>> +{
>> +uint3
Hi Julien,
[...]
>> +static bool get_ttbr_and_gran_64bit(uint64_t *ttbr, unsigned int *gran,
>> +register_t tcr, enum active_ttbr
>> ttbrx)
>> +{
>> +bool disabled;
>> +
>> +if ( ttbrx == TTBR0_ACTIVE )
>> +{
>> +/* Normalize granule size. *
Hi Julien,
[...]
>
> Looking at the code, I see very limited point of having the offsets
> array as you don't use a loop and also use each offset in a single place.
>
>> +((paddr_t)(gva >> 20) & ((1ULL << (12 - n)) - 1)),
>
Don't you think it is more readable to have the GVA offsets at
Hi Julien,
[...]
+
+/*
+ * As we have considered up to 2 MSBs of the GVA for mapping the
first
+ * level translation table, we need to make sure that we limit
the table
+ * offset that is is indexed by GVA<31-n:20> to max 10 bits to
avoid
>
This commit adds functionality to walk the guest's page tables using the
short-descriptor translation table format for both ARMv7 and ARMv8. The
implementation is based on ARM DDI 0487B-a J1-6002 and ARM DDI 0406C-b
B3-1506.
Signed-off-by: Sergej Proskurin
---
Cc: Stefano Stabellini
Cc: J
This commit adds (TCR_|TTBCR_)* defines to simplify access to the
respective register contents. At the same time, we adjust the macros
TCR_T0SZ and TCR_TG0_* by using the newly introduced TCR_T0SZ_SHIFT and
TCR_TG0_SHIFT instead of the hardcoded values.
Signed-off-by: Sergej Proskurin
---
Cc
-step potential translation errors in the function
p2m_mem_access_check_and_get_page due to restricted memory (e.g. to the
guest's page tables themselves), we walk the guest's page tables in
software.
Signed-off-by: Sergej Proskurin
Acked-by: Tamas K Lengyel
---
Cc: Razvan Cojocaru
Cc: Tama
commits.
Signed-off-by: Sergej Proskurin
---
Cc: Stefano Stabellini
Cc: Julien Grall
---
v4: We reused the previous commit with the msg "arm/mem_access: Add
defines holding the width of 32/64bit regs" from v3, as we can reuse
the already existing define BITS_PER_WORD.
v5: I
f such. Please note that this
patch series is based on the second part of Julien Grall's patch series in [1]:
"xen/arm: Move LPAE definition in a separate header".
The following patch series can be found on Github[0].
Cheers,
~Sergej
[0] https://github.com/sergej-proskurin/x
We extend the current implementation by an additional permission,
GV2M_EXEC, which will be used to describe execute permissions of PTE's
as part of our guest translation table walk implementation.
Signed-off-by: Sergej Proskurin
Acked-by: Julien Grall
---
Cc: Stefano Stabellini
Cc: J
M DDI 0487B.a J1-5922, J1-5999, and ARM DDI 0406C.b B3-1510.
Note that the current implementation lacks support for Large VA/PA on
ARMv8.2 architectures (LVA/LPA, 52-bit virtual and physical address
sizes). The associated location in the code is marked appropriately.
Signed-off-by: Sergej Proskurin
-
to use the consolidated defines.
Signed-off-by: Sergej Proskurin
---
Cc: Jan Beulich
---
xen/include/xen/iommu.h | 3 +--
xen/include/xen/lib.h | 4
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/xen/include/xen/iommu.h b/xen/include/xen/iommu.h
index 5803e3f95b..75746e55b0
The current implementation of GENMASK is capable of creating bitmasks of
32-bit values on AArch32 and 64-bit values on AArch64. As we need to
create masks for 64-bit values on AArch32 as well, in this commit we
introduce the GENMASK_ULL bit operation.
Signed-off-by: Sergej Proskurin
---
Cc
The ARMv8 architecture supports pages with different (4K, 16K, and 64K) sizes.
To enable guest page table walks for various configurations, this commit
extends the defines and helpers of the current implementation.
Signed-off-by: Sergej Proskurin
---
Cc: Stefano Stabellini
Cc: Julien Grall
TTBR0_EL1, TTBR1_EL1, and
SCTLR_EL1.
Signed-off-by: Sergej Proskurin
Acked-by: Julien Grall
---
Cc: Stefano Stabellini
Cc: Julien Grall
---
v2: Rename p2m_gva_to_ipa to p2m_walk_gpt and move it to p2m.c.
Move the functionality responsible for walking long-descriptor based
translation tab
This commit introduces a new helper that checks whether the target PTE
holds a page mapping or not. This helper will be used as part of the
following commits.
Signed-off-by: Sergej Proskurin
---
Cc: Stefano Stabellini
Cc: Julien Grall
---
xen/include/asm-arm/lpae.h | 5 +
1 file changed
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