Hi Stefano,
On 27/01/2017 19:27, Stefano Stabellini wrote:
On Thu, 26 Jan 2017, Tamas K Lengyel wrote:
On Thu, Jan 26, 2017 at 10:54 AM, Tamas K Lengyel
wrote:
On Thu, Jan 26, 2017 at 4:30 AM, Julien Grall wrote:
So according to the manual (C5.3.9-10) IALLU and IALLUIS are not
available fro
On Thu, 26 Jan 2017, Tamas K Lengyel wrote:
> On Thu, Jan 26, 2017 at 10:54 AM, Tamas K Lengyel
> wrote:
> > On Thu, Jan 26, 2017 at 4:30 AM, Julien Grall wrote:
> >> (CC xen-devel, Ravzan, and Stefao)
> >>
> >> Hi Tamas,
> >>
> >> Not sure why you only CC me on the answer. I have CCed again xen-
On Thu, Jan 26, 2017 at 10:54 AM, Tamas K Lengyel
wrote:
> On Thu, Jan 26, 2017 at 4:30 AM, Julien Grall wrote:
>> (CC xen-devel, Ravzan, and Stefao)
>>
>> Hi Tamas,
>>
>> Not sure why you only CC me on the answer. I have CCed again xen-devel as I
>> don't see any sensible discussion in it.
>>
>>
On Thu, Jan 26, 2017 at 4:30 AM, Julien Grall wrote:
> (CC xen-devel, Ravzan, and Stefao)
>
> Hi Tamas,
>
> Not sure why you only CC me on the answer. I have CCed again xen-devel as I
> don't see any sensible discussion in it.
>
> On 26/01/2017 00:11, Tamas K Lengyel wrote:
>>
>> On Wed, Jan 25, 2
CC correct e-mail address for Stefano.
On 26/01/2017 11:30, Julien Grall wrote:
(CC xen-devel, Ravzan, and Stefao)
Hi Tamas,
Not sure why you only CC me on the answer. I have CCed again xen-devel
as I don't see any sensible discussion in it.
On 26/01/2017 00:11, Tamas K Lengyel wrote:
On We
(CC xen-devel, Ravzan, and Stefao)
Hi Tamas,
Not sure why you only CC me on the answer. I have CCed again xen-devel
as I don't see any sensible discussion in it.
On 26/01/2017 00:11, Tamas K Lengyel wrote:
On Wed, Jan 25, 2017 at 3:41 PM, Julien Grall wrote:
Hi Tamas,
On 25/01/2017 20:02,
Hi Tamas,
On 25/01/2017 20:02, Tamas K Lengyel wrote:
During an SMC trap it is possible that the user may change the memory
By user, do you mean the monitor application?
from where the SMC was fetched. However, without flushing the icache
the SMC may still trigger if the pCPU was idle during
On 01/25/2017 10:02 PM, Tamas K Lengyel wrote:
> During an SMC trap it is possible that the user may change the memory
> from where the SMC was fetched. However, without flushing the icache
> the SMC may still trigger if the pCPU was idle during the trap. Flush
> the icache to ensure consistency.
>
