On 01/25/2017 10:02 PM, Tamas K Lengyel wrote: > During an SMC trap it is possible that the user may change the memory > from where the SMC was fetched. However, without flushing the icache > the SMC may still trigger if the pCPU was idle during the trap. Flush > the icache to ensure consistency. > > Signed-off-by: Tamas K Lengyel <tamas.leng...@zentific.com>
Fair enough, assuming the ARM maintainers have no objections: Acked-by: Razvan Cojocaru <rcojoc...@bitdefender.com> Thanks, Razvan _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org https://lists.xen.org/xen-devel
