On Thu, Oct 6, 2016 at 11:10 AM, Julien Grall wrote:
>
>
> On 06/10/2016 09:39, Tamas K Lengyel wrote:
>
>>
>>
>> On Thu, Oct 6, 2016 at 3:59 AM, Razvan Cojocaru
>> mailto:rcojoc...@bitdefender.com>> wrote:
>>
>> On 10/05/2016 11:54 PM, Julien Grall wrote:
>> >
>> >
>> > On 05/10/
On 06/10/2016 09:39, Tamas K Lengyel wrote:
On Thu, Oct 6, 2016 at 3:59 AM, Razvan Cojocaru
mailto:rcojoc...@bitdefender.com>> wrote:
On 10/05/2016 11:54 PM, Julien Grall wrote:
>
>
> On 05/10/2016 13:23, Tamas K Lengyel wrote:
>> Hi Julien,
>> It is expected that cer
On Thu, Oct 6, 2016 at 3:59 AM, Razvan Cojocaru
wrote:
> On 10/05/2016 11:54 PM, Julien Grall wrote:
> >
> >
> > On 05/10/2016 13:23, Tamas K Lengyel wrote:
> >> Hi Julien,
> >> It is expected that certain combinations of mem_access flags will put
> >> the domain into unstable condition, resultin
On 10/05/2016 11:54 PM, Julien Grall wrote:
>
>
> On 05/10/2016 13:23, Tamas K Lengyel wrote:
>> Hi Julien,
>> It is expected that certain combinations of mem_access flags will put
>> the domain into unstable condition, resulting in a crash or a hang. As
>> Razvan mentioned, on x86 we can end up
On 05/10/2016 13:23, Tamas K Lengyel wrote:
Hi Julien,
It is expected that certain combinations of mem_access flags will put
the domain into unstable condition, resulting in a crash or a hang. As
Razvan mentioned, on x86 we can end up triggering EPT misconfiguration
with the wrong set of flags.
Hi Julien,
It is expected that certain combinations of mem_access flags will put the
domain into unstable condition, resulting in a crash or a hang. As Razvan
mentioned, on x86 we can end up triggering EPT misconfiguration with the
wrong set of flags. The user of the API is expected to know what he
Hello Julien,
> I have been looking into mem access support on ARM and I am wondering
> how we expect the flags MEM_ACCESS_{R,W,X} to be used when the
> permission fault is happening during stage 1 page table walk.
>
> For instance, if the fault is happening when the processor is loading an
> ins
Hello Tamas and Ravzan,
I have been looking into mem access support on ARM and I am wondering
how we expect the flags MEM_ACCESS_{R,W,X} to be used when the
permission fault is happening during stage 1 page table walk.
For instance, if the fault is happening when the processor is loading an
