Hello Tamas and Ravzan,
I have been looking into mem access support on ARM and I am wondering
how we expect the flags MEM_ACCESS_{R,W,X} to be used when the
permission fault is happening during stage 1 page table walk.
For instance, if the fault is happening when the processor is loading an
instruction, MEM_ACCESS_X will be set. However, the table walker may
have failed because it is not possible to read the entry or update it
(e.g dirty management).
Let say the region has been protected read-write (I think it is
XENMEM_access_x), it means that mem access will think it doesn't have to
deal with the error and bail out. So the guest vCPU will get stuck
forever repeating the stage-1 page table walk and getting an instruction
fault.
Similarly, the bit ESR_EL2.WnR during a data abort indicates whether the
instruction was a load or store and not whether the page table walker
was reading or writing the entry (see more details on [1]).
So what is the expectation of the flags MEM_ACCESS_R (e.g
npfec.read_access) and MEM_ACCESS_W (e.g npfec.write_access) for stage-2
abort on stage-1 page table walk?
Regards,
[1] https://patchwork.kernel.org/patch/9356377/
--
Julien Grall
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