On 08/05/17 07:40, Sergej Proskurin wrote:
Hi Julien,
On 05/02/2017 02:01 PM, Julien Grall wrote:
On 02/05/17 12:56, Julien Grall wrote:
Hi Sergej,
On 30/04/17 20:48, Sergej Proskurin wrote:
The TTBCR_SZ holds only 3 bits and thus must be masked with the value
0x7 instead of the previou
Hi Julien,
On 05/02/2017 02:01 PM, Julien Grall wrote:
>
>
> On 02/05/17 12:56, Julien Grall wrote:
>> Hi Sergej,
>>
>> On 30/04/17 20:48, Sergej Proskurin wrote:
>>> The TTBCR_SZ holds only 3 bits and thus must be masked with the value
>>> 0x7 instead of the previously used value 0xf.
>>
>> Plea
Hi Julien,
On 05/02/2017 01:56 PM, Julien Grall wrote:
> Hi Sergej,
>
> On 30/04/17 20:48, Sergej Proskurin wrote:
>> The TTBCR_SZ holds only 3 bits and thus must be masked with the value
>> 0x7 instead of the previously used value 0xf.
>
> Please quote the spec (paragaph + version) when you do a
On 02/05/17 12:56, Julien Grall wrote:
Hi Sergej,
On 30/04/17 20:48, Sergej Proskurin wrote:
The TTBCR_SZ holds only 3 bits and thus must be masked with the value
0x7 instead of the previously used value 0xf.
Please quote the spec (paragaph + version) when you do a such change.
TTBCR_* fla
Hi Sergej,
On 30/04/17 20:48, Sergej Proskurin wrote:
The TTBCR_SZ holds only 3 bits and thus must be masked with the value
0x7 instead of the previously used value 0xf.
Please quote the spec (paragaph + version) when you do a such change.
TTBCR_* flags are used for both TCR_EL1 (AArch64) and
The TTBCR_SZ holds only 3 bits and thus must be masked with the value
0x7 instead of the previously used value 0xf.
Signed-off-by: Sergej Proskurin
---
Cc: Stefano Stabellini
Cc: Julien Grall
---
xen/include/asm-arm/processor.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
