Hi Sergej,
On 30/04/17 20:48, Sergej Proskurin wrote:
The TTBCR_SZ holds only 3 bits and thus must be masked with the value
0x7 instead of the previously used value 0xf.
Please quote the spec (paragaph + version) when you do a such change.
TTBCR_* flags are used for both TCR_EL1 (AArch64) and TTBCR (AArch32).
Looking at the spec (ARM DDI 0487A.k_iss10775) TCR_EL1.{T0SZ,T1SZ) is
encoded on 6 bits and TTBCR_EL1.{T0SZ,T1SZ} is encoded on 3 bits, with
the following 3 bits RES0.
So the mask here should be 0x3f.
Cheers,
Signed-off-by: Sergej Proskurin <prosku...@sec.in.tum.de>
---
Cc: Stefano Stabellini <sstabell...@kernel.org>
Cc: Julien Grall <julien.gr...@arm.com>
---
xen/include/asm-arm/processor.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index 4fdf86070b..c8b8cff311 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -94,7 +94,7 @@
#define TTBCR_N_2KB _AC(0x03,U)
#define TTBCR_N_1KB _AC(0x04,U)
-#define TTBCR_SZ_MASK 0xf
+#define TTBCR_SZ_MASK _AC(0x7,UL)
/* SCTLR System Control Register. */
/* HSCTLR is a subset of this. */
--
Julien Grall
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