Hi,
On 22/03/17 16:33, Julien Grall wrote:
[ ... ]
gicv3_dist_init();
+res = gicv3_its_init();
+if ( res )
+printk(XENLOG_WARNING "GICv3: ITS: initialization failed:
%d\n", res);
>>>
>>> I would have expect a panic here because the ITS subsystem could
On 22/03/17 16:08, André Przywara wrote:
Hi,
Hi Andre,
On 22/03/17 13:52, Julien Grall wrote:
Hi Andre,
On 03/16/2017 11:20 AM, Andre Przywara wrote:
Each ITS maps a pair of a DeviceID (for instance derived from a PCI
b/d/f triplet) and an EventID (the MSI payload or interrupt ID) to a
Hi,
On 22/03/17 13:52, Julien Grall wrote:
> Hi Andre,
>
> On 03/16/2017 11:20 AM, Andre Przywara wrote:
>> Each ITS maps a pair of a DeviceID (for instance derived from a PCI
>> b/d/f triplet) and an EventID (the MSI payload or interrupt ID) to a
>> pair of LPI number and collection ID, which po
Hi Andre,
On 03/16/2017 11:20 AM, Andre Przywara wrote:
Each ITS maps a pair of a DeviceID (for instance derived from a PCI
b/d/f triplet) and an EventID (the MSI payload or interrupt ID) to a
pair of LPI number and collection ID, which points to the target CPU.
This mapping is stored in the dev
On Thu, 16 Mar 2017, Andre Przywara wrote:
> Each ITS maps a pair of a DeviceID (for instance derived from a PCI
> b/d/f triplet) and an EventID (the MSI payload or interrupt ID) to a
> pair of LPI number and collection ID, which points to the target CPU.
> This mapping is stored in the device and
Each ITS maps a pair of a DeviceID (for instance derived from a PCI
b/d/f triplet) and an EventID (the MSI payload or interrupt ID) to a
pair of LPI number and collection ID, which points to the target CPU.
This mapping is stored in the device and collection tables, which software
has to provide fo
