flight 109930 ovmf real [real]
http://logs.test-lab.xenproject.org/osstest/logs/109930/
Perfect :-)
All tests in this flight passed as required
version targeted for testing:
ovmf 76d1c752cb6629262bb999204f574e274be00500
baseline version:
ovmf a6b5380642c4d9f55175d
On 06/01/2017 11:50 PM, Paratey, Swapnil wrote:
So you may have noticed that I did commit this, but then I had to
revert it again, as it breaks the build on ARM. Didn't you need the
change specifically for ARM? If so, how come you didn't build test
it there?
I would be surprised if this cha
On 17-06-01 04:45:58, Jan Beulich wrote:
> >>> On 01.06.17 at 12:00, wrote:
> > On 17-05-30 08:32:59, Jan Beulich wrote:
> >> >>> On 03.05.17 at 10:44, wrote:
> >> > --- a/xen/arch/x86/psr.c
> >> > +++ b/xen/arch/x86/psr.c
> >> > @@ -118,11 +118,13 @@ static const struct feat_props {
> >> > *
Should I submit a v8 with the "CONFIG_HAS_PCI" macro specifications for
the case statements? I apologize for not trying the build for ARM
beforehand.
Yes please.
~Andrew
Should the contents of "enum serial_param_type" and
"static const struct serial_param_var __initconst sp_vars[]" also be s
On Thu, 2017-06-01 at 20:08 +0100, Andrew Cooper wrote:
> On 01/06/17 18:34, Dario Faggioli wrote:
> > diff --git a/xen/common/spinlock.c b/xen/common/spinlock.c
> > index 2a06406..33b903e 100644
> > --- a/xen/common/spinlock.c
> > +++ b/xen/common/spinlock.c
> > @@ -150,7 +150,9 @@ void _spin_lock
Since the SCSI core zeroes driver-private command data, remove
that code from the xen-scsifront driver.
Signed-off-by: Bart Van Assche
Reviewed-by: Hannes Reinecke
Reviewed-by: Juergen Gross
Cc: xen-de...@lists.xenproject.org
Cc: Johannes Thumshirn
---
drivers/scsi/xen-scsifront.c | 1 -
1 fi
On Thu, 2017-06-01 at 19:02 +0100, Andrew Cooper wrote:
> On 01/06/17 18:33, Dario Faggioli wrote:
> > More specifically:
> > - the handling of the TRC_HW_IRQ_HANDLED is fixed, both in
> > xentrace_format and in xenalyze;
> > - simple events for recording when we enter and exit the
> > do_I
On Thu, 2017-06-01 at 18:53 +0100, Andrew Cooper wrote:
> On 01/06/17 18:33, Dario Faggioli wrote:
> > diff --git a/xen/common/trace.c b/xen/common/trace.c
> > index 4fedc26..f29cd4c 100644
> > --- a/xen/common/trace.c
> > +++ b/xen/common/trace.c
> > @@ -691,7 +691,8 @@ void __trace_var(u32 event,
On 01/06/2017 23:50, Paratey, Swapnil wrote:
>
>>> So you may have noticed that I did commit this, but then I had to
>>> revert it again, as it breaks the build on ARM. Didn't you need the
>>> change specifically for ARM? If so, how come you didn't build test
>>> it there?
>>
>> I would be surprise
So you may have noticed that I did commit this, but then I had to
revert it again, as it breaks the build on ARM. Didn't you need the
change specifically for ARM? If so, how come you didn't build test
it there?
I would be surprised if this change is necessary for ARM as we don't
support com1.
> @@ -696,7 +777,7 @@ int hvm_do_IRQ_dpci(struct domain *d, struct pirq *pirq)
> struct hvm_irq_dpci *dpci = domain_get_irq_dpci(d);
> struct hvm_pirq_dpci *pirq_dpci = pirq_dpci(pirq);
>
> -if ( !iommu_enabled || !dpci || !pirq_dpci ||
> +if ( !iommu_enabled || (!is_hardware_d
On Fri, 26 May 2017, Boris Ostrovsky wrote:
> On 05/19/2017 07:22 PM, Stefano Stabellini wrote:
> > Introduce a per-frontend data structure named pvcalls_back_priv. It
> > contains pointers to the command ring, its event channel, a list of
> > active sockets and a tree of passive sockets (passing s
On 01/06/2017 21:41, Boris Ostrovsky wrote:
On 06/01/2017 11:38 AM, Julien Grall wrote:
Hi Boris,
On 01/06/17 16:16, Boris Ostrovsky wrote:
On 06/01/2017 10:01 AM, Julien Grall wrote:
Hi Boris,
On 01/06/17 14:33, Boris Ostrovsky wrote:
On 06/01/2017 08:50 AM, Julien Grall wrote:
Hi Boris
On Thu, 25 May 2017, Boris Ostrovsky wrote:
> On 05/19/2017 07:22 PM, Stefano Stabellini wrote:
> > Introduce the C header file which defines the PV Calls interface. It is
> > imported from xen/include/public/io/pvcalls.h.
> >
> > Signed-off-by: Stefano Stabellini
> > CC: konrad.w...@oracle.com
>
On Thu, 25 May 2017, Boris Ostrovsky wrote:
> On 05/19/2017 07:22 PM, Stefano Stabellini wrote:
> > Introduce the code to handle xenbus state changes.
> >
> > Implement the probe function for the pvcalls backend. Write the
> > supported versions, max-page-order and function-calls nodes to xenstore,
On 06/01/2017 11:38 AM, Julien Grall wrote:
> Hi Boris,
>
> On 01/06/17 16:16, Boris Ostrovsky wrote:
>> On 06/01/2017 10:01 AM, Julien Grall wrote:
>>> Hi Boris,
>>>
>>> On 01/06/17 14:33, Boris Ostrovsky wrote:
On 06/01/2017 08:50 AM, Julien Grall wrote:
> Hi Boris,
>
> On 31/05/
On 01/06/17 18:34, Dario Faggioli wrote:
> Trace when interrupts are disabled and (re)enabled.
> Basically, we replace the IRQ disabling and enabling
> functions with helpers that does the same, but also
> output the proper trace record.
>
> For putting in the record something that will let
> us id
On 01/06/17 18:34, Dario Faggioli wrote:
> And compile it out of the hypervisor entirely.
>
> Code and other sections' sizes change as follows.
>
> Output of `size`:
> vanilla patched-Y patched-N
> text 192900719290071902783
> data 337784 337784 337688
> bss 1310464
This run is configured for baseline tests only.
flight 71466 qemu-mainline real [real]
http://osstest.xs.citrite.net/~osstest/testlogs/logs/71466/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-amd64-i386-xl-qemuu-win7-amd64 15 guest-l
On Thu, 1 Jun 2017, George Dunlap wrote:
> > On May 31, 2017, at 6:45 PM, Stefano Stabellini
> > wrote:
> >
> > On Wed, 31 May 2017, George Dunlap wrote:
> >> On 30/05/17 18:29, Stefano Stabellini wrote:
> >>> On Fri, 26 May 2017, Volodymyr Babchuk wrote:
> >>> The other issue with stubdoms
flight 109929 xen-unstable-smoke real [real]
http://logs.test-lab.xenproject.org/osstest/logs/109929/
Failures :-/ but no regressions.
Tests which did not succeed, but are not blocking:
test-arm64-arm64-xl-xsm 1 build-check(1) blocked n/a
test-amd64-amd64-libvirt 12 mig
Hi Andre,
On 26/05/17 18:35, Andre Przywara wrote:
Emulate the memory mapped ITS registers and provide a stub to introduce
the ITS command handling framework (but without actually emulating any
commands at this time).
This fixes a misnomer in our virtual ITS structure, where the spec is
confusin
On 01/06/17 18:33, Dario Faggioli wrote:
> More specifically:
> - the handling of the TRC_HW_IRQ_HANDLED is fixed, both in
>xentrace_format and in xenalyze;
> - simple events for recording when we enter and exit the
>do_IRQ function, as well as when we deal with a guest
>IRQ, are adde
On 01/06/17 18:57, Andrew Cooper wrote:
On 01/06/17 18:55, Julien Grall wrote:
Hi Andrew,
On 26/05/17 18:03, Andrew Cooper wrote:
These bugfixes finally allow my comprehensive XTF test (following
several
bugfixes, and the added feature of the 0-level pagetable tests) to
complete
successfully o
Hi,
On 26/05/17 07:02, Jan Beulich wrote:
On 25.05.17 at 20:00, wrote:
On 05/25/2017 01:46 PM, Julien Grall wrote:
On 25/05/17 18:08, Boris Ostrovsky wrote:
Is this:
https://lists.xenproject.org/archives/html/xen-devel/2017-05/msg02340.html
being deferred to the next RC (if we are having
On 01/06/17 18:55, Julien Grall wrote:
> Hi Andrew,
>
> On 26/05/17 18:03, Andrew Cooper wrote:
>> These bugfixes finally allow my comprehensive XTF test (following
>> several
>> bugfixes, and the added feature of the 0-level pagetable tests) to
>> complete
>> successfully on a Skylake Server syste
On 01/06/17 18:33, Dario Faggioli wrote:
> In fact, when calling __trace_var() directly, we can
> assume that tb_init_done has been checked to be true,
> and the if is hence redundant.
>
> While there, also:
> - still in __trace_var(), move the check that the event
>is actually being traced up
Hi Andrew,
On 26/05/17 18:03, Andrew Cooper wrote:
These bugfixes finally allow my comprehensive XTF test (following several
bugfixes, and the added feature of the 0-level pagetable tests) to complete
successfully on a Skylake Server system, with PKU.
I know this is getting very tight to the li
On 01/06/17 18:25, Julien Grall wrote:
> CC Ian + Wei for the testing
>
> On 01/06/17 12:21, Jan Beulich wrote:
> On 01.06.17 at 13:18, wrote:
>>> Hi Jan,
>>>
>>> On 01/06/17 12:15, Jan Beulich wrote:
>>> On 01.06.17 at 13:09, wrote:
> Hi Andrew,
>
> On 31/05/17 14:23, Andrew
Hi,
On 01/06/17 12:14, Jan Beulich wrote:
On 01.06.17 at 13:06, wrote:
On 31/05/17 08:51, Jan Beulich wrote:
While f32400e90c ("x86: fix build with gcc 7")'s change to
compat_array_access_ok() is necessary, I had blindly and needlessly
also added it to array_access_ok(). There's no conditiona
Making it possible generate events showing the
activity and the behavior of timers.
Gate this with its specific Kconfig option (under
CONFIG_TRACING), and keep it in disabled state by
default.
---
Cc: George Dunlap
Cc: Andrew Cooper
Cc: Jan Beulich
Cc: Konrad Rzeszutek Wilk
Cc: Stefano Stabell
Signed-off-by: Dario Faggioli
---
Cc: George Dunlap
Cc: Ian Jackson
Cc: Wei Liu
---
tools/xentrace/formats|7 +++
tools/xentrace/xenalyze.c | 92 +
2 files changed, 99 insertions(+)
diff --git a/tools/xentrace/formats b/tools/xentrace/form
Signed-off-by: Dario Faggioli
---
Cc: George Dunlap
Cc: Ian Jackson
Cc: Wei Liu
---
tools/xentrace/formats| 10 +++
tools/xentrace/xenalyze.c | 141 +
2 files changed, 151 insertions(+)
diff --git a/tools/xentrace/formats b/tools/xentrace/for
Making it possible generate events showing the
activity and the behavior of tasklets.
Gate this with its specific Kconfig option (under
CONFIG_TRACING), and keep it in disabled state by
default.
---
Cc: George Dunlap
Cc: Andrew Cooper
Cc: Jan Beulich
Cc: Konrad Rzeszutek Wilk
Cc: Stefano Stabe
Signed-off-by: Dario Faggioli
---
Cc: George Dunlap
Cc: Ian Jackson
Cc: Wei Liu
---
tools/xentrace/analyze.h |1
tools/xentrace/formats|9
tools/xentrace/xenalyze.c | 114 +
3 files changed, 123 insertions(+), 1 deletion(-)
diff
so the trace will show properly decoded info,
rather than just a bunch of hex codes.
Signed-off-by: Dario Faggioli
---
Cc: George Dunlap
Cc: Andrew Cooper
Cc: Ian Jackson
Cc: Wei Liu
Cc: Jennifer Herbert
---
tools/xentrace/formats|2 ++
tools/xentrace/xenalyze.c | 16 +
Signed-off-by: Dario Faggioli
---
Cc: George Dunlap
Cc: Ian Jackson
Cc: Wei Liu
---
tools/xentrace/formats|5 +++
tools/xentrace/xenalyze.c | 82 +
2 files changed, 87 insertions(+)
diff --git a/tools/xentrace/formats b/tools/xentrace/form
Making it possible generate events showing the
activity and the behavior of the softirq subsystem.
Gate this with its specific Kconfig option (under
CONFIG_TRACING), and keep it in disabled state by
default.
---
Cc: George Dunlap
Cc: Andrew Cooper
Cc: Jan Beulich
Cc: Konrad Rzeszutek Wilk
Cc:
Making it possible generate events showing the
activity and the behavior of the RCU subsystem.
Gate this with its specific Kconfig option (under
CONFIG_TRACING), and keep it in disabled state by
default.
---
Cc: George Dunlap
Cc: Andrew Cooper
Cc: Jan Beulich
Cc: Konrad Rzeszutek Wilk
Cc: Stef
And compile it out of the hypervisor entirely.
Code and other sections' sizes change as follows.
Output of `size`:
vanilla patched-Y patched-N
text 192900719290071902783
data 337784 337784 337688
bss 131046413104641310336
Output of `size -A`:
vani
Trace when interrupts are disabled and (re)enabled.
Basically, we replace the IRQ disabling and enabling
functions with helpers that does the same, but also
output the proper trace record.
For putting in the record something that will let
us identify _where_ in the code (i.e., in what function)
th
In fact, not all the information present in the trace
record were used and printed.
Signed-off-by: Dario Faggioli
---
George Dunlap
Ian Jackson
Wei Liu
---
tools/xentrace/xenalyze.c | 24 +++-
1 file changed, 19 insertions(+), 5 deletions(-)
diff --git a/tools/xentrace/
More specifically:
- the handling of the TRC_HW_IRQ_HANDLED is fixed, both in
xentrace_format and in xenalyze;
- simple events for recording when we enter and exit the
do_IRQ function, as well as when we deal with a guest
IRQ, are added;
- tracing of IRQs handled with direct vectors is
In fact, when calling __trace_var() directly, we can
assume that tb_init_done has been checked to be true,
and the if is hence redundant.
While there, also:
- still in __trace_var(), move the check that the event
is actually being traced up a little bit (to bail as
soon as possible, if it i
Hello,
While chasing and dealing with bugs, over this last period, I've found myself
augmenting Xen with quite a few new tracing capabilities, especially focusing
on:
- IRQ being disabled and (re)enabled (in addition to the already existing
tracing of IRQ related activity that we have);
- RCU
In fact, right now, we read it at every iteration of the loop.
The reason it's done like this is how context switch was handled
on IA64 (see commit ae9bfcdc, "[XEN] Various softirq cleanups" [1]).
However:
1) we don't have IA64 any longer, and all the achitectures that
we do support, are ok wit
CC Ian + Wei for the testing
On 01/06/17 12:21, Jan Beulich wrote:
On 01.06.17 at 13:18, wrote:
Hi Jan,
On 01/06/17 12:15, Jan Beulich wrote:
On 01.06.17 at 13:09, wrote:
Hi Andrew,
On 31/05/17 14:23, Andrew Cooper wrote:
On 31/05/17 09:52, Julien Grall wrote:
Hi,
On 05/22/2017 02:32 P
Hi,
Can someone explain, why evtchn_fifo_unmask() requires irqs_disabled().
What happens, if irqs are not disabled ?
Thanks,
Anoob.
___
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
Hi,
On 01/06/17 14:11, Wei Liu wrote:
On Thu, Jun 01, 2017 at 02:10:50PM +0100, Andrew Cooper wrote:
The number of buffers is ahead of the buffer list in the argument list.
Signed-off-by: Andrew Cooper
Acked-by: Wei Liu
In general I am happy with any documentation update for Xen 4.9:
Re
From the context calling pi_desc_init(), we can conclude the current
implementation of VT-d PI depends on CPU-side PI. If we disable APICv
but enable VT-d PI explicitly in xen boot command line, we would get
an assertion failure.
This patch disables VT-d PI when APICv is disabled and adds some
rel
Hi Boris,
On 01/06/17 16:16, Boris Ostrovsky wrote:
On 06/01/2017 10:01 AM, Julien Grall wrote:
Hi Boris,
On 01/06/17 14:33, Boris Ostrovsky wrote:
On 06/01/2017 08:50 AM, Julien Grall wrote:
Hi Boris,
On 31/05/17 14:54, Boris Ostrovsky wrote:
On 05/31/2017 09:03 AM, Julien Grall wrote:
C
On Thu, Jun 01, 2017 at 03:40:07PM +0100, Andrew Cooper wrote:
> On 01/06/17 12:49, Roger Pau Monne wrote:
> > Move the code to allocate and map a domain pirq (either GSI or MSI)
> > into the x86 irq code base, so that it can be used outside of the
> > physdev ops.
> >
> > This change shouldn't aff
This commit adds two defines holding the register width of 32 bit and 64 bit
registers. These defines simplify using the associated constants in the
following commits.
Signed-off-by: Sergej Proskurin
---
Cc: Stefano Stabellini
Cc: Julien Grall
---
xen/include/asm-arm/processor.h | 4
1 fi
In this commit, we make use of the gpt walk functionality introduced in the
previous commits. If mem_access is active, hardware-based gva to ipa
translation might fail, as gva_to_ipa uses the guest's translation tables,
access to which might be restricted by the active VTTBR. To side-step potential
This commit adds functionality to walk the guest's page tables using the
short-descriptor translation table format for both ARMv7 and ARMv8. The
implementation is based on ARM DDI 0487A-g G4-4189 and ARM DDI 0406C-b
B3-1506.
Signed-off-by: Sergej Proskurin
---
Cc: Stefano Stabellini
Cc: Julien G
The function p2m_mem_access_check_and_get_page in mem_access.c translates a gva
to an ipa by means of the hardware functionality of the ARM architecture. This
is implemented in the function gva_to_ipa. If mem_access is active,
hardware-based gva to ipa translation might fail, as gva_to_ipa uses the
This commit adds (TCR_|TTBCR_)* defines to simplify access to the respective
register contents.
Signed-off-by: Sergej Proskurin
---
Cc: Stefano Stabellini
Cc: Julien Grall
---
v2: Define TCR_SZ_MASK in a way so that it can be also applied to 32-bit guests
using the long-descriptor translati
This commit adds functionality to walk the guest's page tables using the
long-descriptor translation table format for both ARMv7 and ARMv8.
Similar to the hardware architecture, the implementation supports
different page granularities (4K, 16K, and 64K). The implementation is
based on ARM DDI 0487A
The function p2m_mem_access_check_and_get_page in mem_access.c translates a gva
to an ipa by means of the hardware functionality of the ARM architecture. This
is implemented in the function gva_to_ipa. If mem_access is active,
hardware-based gva to ipa translation might fail, as gva_to_ipa uses the
Hi all,
The function p2m_mem_access_check_and_get_page is called from the function
get_page_from_gva if mem_access is active and the hardware-aided translation of
the given guest virtual address (gva) into machine address fails. That is, if
the stage-2 translation tables constrain access to the gu
This commit adds functionality to walk the guest's page tables using the
short-descriptor translation table format for both ARMv7 and ARMv8. The
implementation is based on ARM DDI 0487A-g G4-4189 and ARM DDI 0406C-b
B3-1506.
Signed-off-by: Sergej Proskurin
---
Cc: Stefano Stabellini
Cc: Julien G
In this commit, we make use of the gpt walk functionality introduced in the
previous commits. If mem_access is active, hardware-based gva to ipa
translation might fail, as gva_to_ipa uses the guest's translation tables,
access to which might be restricted by the active VTTBR. To side-step potential
This commit adds two defines holding the register width of 32 bit and 64 bit
registers. These defines simplify using the associated constants in the
following commits.
Signed-off-by: Sergej Proskurin
---
Cc: Stefano Stabellini
Cc: Julien Grall
---
xen/include/asm-arm/processor.h | 4
1 fi
This commit adds (TCR_|TTBCR_)* defines to simplify access to the respective
register contents.
Signed-off-by: Sergej Proskurin
---
Cc: Stefano Stabellini
Cc: Julien Grall
---
v2: Define TCR_SZ_MASK in a way so that it can be also applied to 32-bit guests
using the long-descriptor translati
The ARMv8 architecture supports pages with different (4K, 16K, and 64K) sizes.
To enable guest page table walks for various configurations, this commit
extends the defines and helpers of the current implementation.
Signed-off-by: Sergej Proskurin
---
Cc: Stefano Stabellini
Cc: Julien Grall
---
The current implementation does not provide appropriate types for
short-descriptor translation table entries. As such, this commit adds new
types, which simplify managing the respective translation table entries.
Signed-off-by: Sergej Proskurin
---
Cc: Stefano Stabellini
Cc: Julien Grall
---
x
The current implementation does not provide appropriate types for
short-descriptor translation table entries. As such, this commit adds new
types, which simplify managing the respective translation table entries.
Signed-off-by: Sergej Proskurin
---
Cc: Stefano Stabellini
Cc: Julien Grall
---
x
This commit adds functionality to walk the guest's page tables using the
long-descriptor translation table format for both ARMv7 and ARMv8.
Similar to the hardware architecture, the implementation supports
different page granularities (4K, 16K, and 64K). The implementation is
based on ARM DDI 0487A
The ARMv8 architecture supports pages with different (4K, 16K, and 64K) sizes.
To enable guest page table walks for various configurations, this commit
extends the defines and helpers of the current implementation.
Signed-off-by: Sergej Proskurin
---
Cc: Stefano Stabellini
Cc: Julien Grall
---
On 06/01/2017 10:01 AM, Julien Grall wrote:
> Hi Boris,
>
> On 01/06/17 14:33, Boris Ostrovsky wrote:
>> On 06/01/2017 08:50 AM, Julien Grall wrote:
>>> Hi Boris,
>>>
>>> On 31/05/17 14:54, Boris Ostrovsky wrote:
On 05/31/2017 09:03 AM, Julien Grall wrote:
> Commit 5995a68 "xen/privcmd: Ad
On 01/06/17 13:40, Dario Faggioli wrote:
> On Thu, 2017-06-01 at 12:52 +0200, George Dunlap wrote:
>>> On May 31, 2017, at 6:45 PM, Stefano Stabellini >> .org> wrote:
>>>
>>> I don't think we should provide that. If the user wants a stable
>>> interface, she can use domains. I suggested that the co
On Thu, Jun 01, 2017 at 07:17:16AM -0600, Jan Beulich wrote:
> >>> On 01.06.17 at 13:49, wrote:
> > --- a/xen/include/public/domctl.h
> > +++ b/xen/include/public/domctl.h
> > @@ -559,7 +559,6 @@ typedef enum pt_irq_type_e {
> > struct xen_domctl_bind_pt_irq {
> > uint32_t machine_irq;
> >
On 01/06/17 12:49, Roger Pau Monne wrote:
> Move the code to allocate and map a domain pirq (either GSI or MSI)
> into the x86 irq code base, so that it can be used outside of the
> physdev ops.
>
> This change shouldn't affect the functionality of the already existing
> physdev ops.
>
> Signed-off
On 01/06/17 13:27, Jan Beulich wrote:
> Also drop a stray initializer.
>
> Signed-off-by: Jan Beulich
Acked-by: George Dunlap
>
> --- a/xen/arch/x86/mm/hap/hap.c
> +++ b/xen/arch/x86/mm/hap/hap.c
> @@ -248,8 +248,7 @@ static void hap_clean_dirty_bitmap(struc
> /**
>>> On 01.06.17 at 13:49, wrote:
> Move the code to allocate and map a domain pirq (either GSI or MSI)
> into the x86 irq code base, so that it can be used outside of the
> physdev ops.
>
> This change shouldn't affect the functionality of the already existing
> physdev ops.
>
> Signed-off-by: R
On Thursday, 1 June 2017 11:56:28 PM AEST Boris Ostrovsky wrote:
> On 05/31/2017 10:25 PM, Steven Haigh wrote:
> > On 2017-05-31 00:37, Steven Haigh wrote:
> >> On 31/05/17 00:18, Boris Ostrovsky wrote:
> >>> On 05/30/2017 06:27 AM, Steven Haigh wrote:
> Just wanted to give this a nudge to try
Hi Boris,
On 01/06/17 14:33, Boris Ostrovsky wrote:
On 06/01/2017 08:50 AM, Julien Grall wrote:
Hi Boris,
On 31/05/17 14:54, Boris Ostrovsky wrote:
On 05/31/2017 09:03 AM, Julien Grall wrote:
Commit 5995a68 "xen/privcmd: Add support for Linux 64KB page
granularity" did
not go far enough to s
>>> On 31.05.17 at 14:41, wrote:
> According to SDM Chapter ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
> -> Extended XAPIC (x2APIC) -> x2APIC State Transitions, The existing code to
> handle guest's writing MSR_IA32_APICBASE has two flaws:
> 1. Transition from x2APIC Mode to Disabled Mode i
Hi Bhupinder,
On 01/06/17 14:34, Bhupinder Thakur wrote:
On 26 May 2017 at 19:12, Bhupinder Thakur wrote:
+
+switch ( vpl011_reg )
+{
+case DR:
As mentioned above, you could do:
{
uint8_t ch;
}
+vpl011_read_data(v->domain, &ch);
+*r = ch;
Ple
On 05/31/2017 10:25 PM, Steven Haigh wrote:
> On 2017-05-31 00:37, Steven Haigh wrote:
>> On 31/05/17 00:18, Boris Ostrovsky wrote:
>>> On 05/30/2017 06:27 AM, Steven Haigh wrote:
Just wanted to give this a nudge to try and get some suggestions on
where to go / what to do about this.
Hi Julien,
On 26 May 2017 at 19:12, Bhupinder Thakur wrote:
>>> +
>>> +switch ( vpl011_reg )
>>> +{
>>> +case DR:
>>
>>
>> As mentioned above, you could do:
>>
>> {
>> uint8_t ch;
>>
>> }
>>
>>> +vpl011_read_data(v->domain, &ch);
>>> +*r = ch;
>>
>>
>> P
On 06/01/2017 08:50 AM, Julien Grall wrote:
> Hi Boris,
>
> On 31/05/17 14:54, Boris Ostrovsky wrote:
>> On 05/31/2017 09:03 AM, Julien Grall wrote:
>>> Commit 5995a68 "xen/privcmd: Add support for Linux 64KB page
>>> granularity" did
>>> not go far enough to support 64KB in mmap_batch_fn.
>>>
>>>
>>> On 31.05.17 at 16:14, wrote:
> Update hpet_broadcast_{enter,exit}() to use this_cpu() rather than per_cpu()
> for clarity,
I'm afraid this makes things worse in other respects (see below).
> @@ -697,8 +696,9 @@ void hpet_broadcast_enter(void)
> {
> unsigned int cpu = smp_processor_id()
On 01/06/17 13:27, Jan Beulich wrote:
> Also drop a stray initializer.
>
> Signed-off-by: Jan Beulich
Reviewed-by: Andrew Cooper
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>>> On 01.06.17 at 13:49, wrote:
> --- a/xen/include/public/domctl.h
> +++ b/xen/include/public/domctl.h
> @@ -559,7 +559,6 @@ typedef enum pt_irq_type_e {
> struct xen_domctl_bind_pt_irq {
> uint32_t machine_irq;
> pt_irq_type_t irq_type;
> -uint32_t hvm_domid;
>
> union {
>
On Thu, Jun 01, 2017 at 02:10:50PM +0100, Andrew Cooper wrote:
> The number of buffers is ahead of the buffer list in the argument list.
>
> Signed-off-by: Andrew Cooper
Acked-by: Wei Liu
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The number of buffers is ahead of the buffer list in the argument list.
Signed-off-by: Andrew Cooper
---
CC: George Dunlap
CC: Ian Jackson
CC: Jan Beulich
CC: Konrad Rzeszutek Wilk
CC: Stefano Stabellini
CC: Tim Deegan
CC: Wei Liu
CC: Paul Durrant
CC: Julien Grall
For 4.9. This is only
This run is configured for baseline tests only.
flight 71465 ovmf real [real]
http://osstest.xs.citrite.net/~osstest/testlogs/logs/71465/
Failures :-/ but no regressions.
Regressions which are regarded as allowable (not blocking):
build-amd64-libvirt 5 libvirt-buildfai
flight 109898 qemu-mainline real [real]
http://logs.test-lab.xenproject.org/osstest/logs/109898/
Failures :-/ but no regressions.
Regressions which are regarded as allowable (not blocking):
test-armhf-armhf-xl-rtds15 guest-start/debian.repeat fail REGR. vs. 109701
Tests which did not succee
>>> On 31.05.17 at 14:14, wrote:
> On 31/05/17 08:23, Jan Beulich wrote:
>> -if ((vmcb->_cr3 & 0x7) != 0) {
>> -PRINTF("CR3: MBZ bits are set (%#"PRIx64")\n", vmcb->_cr3);
>> -}
>> -if ((vmcb->_efer & EFER_LMA) && (vmcb->_cr3 & 0xfe) != 0) {
>> -PRINTF("CR3: MBZ bits ar
Hi Boris,
On 31/05/17 14:54, Boris Ostrovsky wrote:
On 05/31/2017 09:03 AM, Julien Grall wrote:
Commit 5995a68 "xen/privcmd: Add support for Linux 64KB page granularity" did
not go far enough to support 64KB in mmap_batch_fn.
The variable 'nr' is the number of 4KB chunk to map. However, when L
On Thu, 2017-06-01 at 12:52 +0200, George Dunlap wrote:
> > On May 31, 2017, at 6:45 PM, Stefano Stabellini > .org> wrote:
> >
> > I don't think we should provide that. If the user wants a stable
> > interface, she can use domains. I suggested that the code for the
> > EL0
> > app should come out
On 01/06/17 11:33, Bhupinder Thakur wrote:
Hi Julien,
Hi Bhupinder,
On 22 May 2017 at 19:54, Julien Grall wrote:
+static const struct mmio_handler_ops vpl011_mmio_handler = {
+.read = vpl011_mmio_read,
+.write = vpl011_mmio_write,
+};
+
+int vpl011_map_guest_page(struct domain *d,
Also drop a stray initializer.
Signed-off-by: Jan Beulich
--- a/xen/arch/x86/mm/hap/hap.c
+++ b/xen/arch/x86/mm/hap/hap.c
@@ -248,8 +248,7 @@ static void hap_clean_dirty_bitmap(struc
//
static struct page_info *hap_alloc(struct domain *d)
{
-
Commit aac1df3d03 ("x86/HVM: introduce hvm_get_cpl() and respective
hook") went too far in one aspect: When emulating a task switch we
really shouldn't be looking at what hvm_get_cpl() returns, as we're
switching all segment registers.
However, instead of reverting the relevant parts of that commi
>>> On 01.06.17 at 13:22, wrote:
> On 01/06/17 11:51, Jan Beulich wrote:
>> While this perhaps is a worthwhile addition, my original request
>> really was to make more visible around the place where it matters
>> that the NX bit is part of the reserved ones when NX is off. Hence
>> I'm not sure th
On Thu, Jun 01, 2017 at 12:49:11PM +0100, Roger Pau Monne wrote:
> This filed is unused and serves no purpose.
>
> Signed-off-by: Roger Pau Monné
> Reported by: Jan Beulich
Missing dash.
Acked-by: Wei Liu
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Move the code to allocate and map a domain pirq (either GSI or MSI)
into the x86 irq code base, so that it can be used outside of the
physdev ops.
This change shouldn't affect the functionality of the already existing
physdev ops.
Signed-off-by: Roger Pau Monné
---
Cc: Jan Beulich
Cc: Andrew Co
Add the glue in order to bind the PVH Dom0 GSI from bare metal. This
is done when Dom0 unmasks the vIO APIC pins, by fetching the current
pin settings and setting up the PIRQ, which will then be bound to
Dom0.
Signed-off-by: Roger Pau Monné
---
Cc: Jan Beulich
Cc: Andrew Cooper
---
Changes sinc
This filed is unused and serves no purpose.
Signed-off-by: Roger Pau Monné
Reported by: Jan Beulich
---
Cc: Ian Jackson
Cc: Wei Liu
Cc: Jan Beulich
---
Changes since v3:
- New in this version.
---
tools/libxc/xc_domain.c | 4
xen/include/public/domctl.h | 1 -
2 files changed, 5 de
1 - 100 of 137 matches
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