Hi
We are trying to update to UHD-4.7 from UHD-4.0 and have rebuilt an out-of-tree
NOC block that works ok in UHD-4.0.
I am looking for some hints to try and resolve this.
Power off and on does not seem to get as clean result as when I issue this
reset.
Hi Martin,
Thank you for your reply. Understood. We are making some changes and will
get back to you.
kind regards,
Marino
On Wed, 6 Nov 2024 at 09:17, Martin Braun wrote:
> Sorry if unclear, I meant hard to debug just by looking at this screenshot.
>
> --M
>
> On Wed, Nov 6, 2024 at 10:17 AM
Hi All
I would like to read the FPGA core temperature of the Kintex within the
USRP2974, and any other temperature sensor available, ideally on the RF
boards.
Is there an API for this?
thanks
marino
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Thanks Marcus. I could not find any temperature sensors :(
On Thu, 15 Jun 2023 at 14:33, Marcus D. Leech
wrote:
> On 15/06/2023 06:31, cyberphox wrote:
> > Hi All
> >
> > I would like to read the FPGA core temperature of the Kintex within
> > the USRP2974, and a
w ADC code from the XADC. To convert that to a temperature, use this
> equation:
>
> Temperature(°C) = XADC_Code * 503.975 / 4096 - 273.15
>
> Thanks,
>
> Wade
>
>
> On Wed, Jun 21, 2023 at 7:45 AM cyberphox wrote:
>
>> Thanks Marcus. I could not find any temperature s
Hi all,
I have a USRP where I have a problem accessing the FPGA to program it.
Normally we use image loader like so:
uhd_image_loader --args="type=x300,addr=192.168.40.2"
--fpga-path="AnFpgaImage.bit"
If I bring up enp1s0f0 like so:
sudo ifconfig enp1s0f0 192.168.40.1 netmask 255.255.255.0
Onc
Hi Marcus,
We are doing this from the embedded host PC, not from the 10G connection
externally
Thank you
On Thu, 13 Jul 2023 at 19:17, Marcus D. Leech
wrote:
> On 13/07/2023 13:20, cyberphox wrote:
>
> Hi all,
>
> I have a USRP where I have a problem accessing the FPG
Hi all,
We have built our own RFNOC block and are trying to do a clean build and
compare the generated bit file against the original files from the FPGA
developer.
I would like to know if the bitfile generated has some dependency with the
GIT commit in some way.
Basically if I take the file chan
Hi All,
I have recently taken the plunge and updated from UHD 4.0 to UHD 4.7 and
have encountered an error when trying to build the FPGA with a custom NOC
block. This is what I get right after issuing the build command:
Traceback (most recent call last):
File "/usr/local/bin/rfnoc_image_builder
Hi All,
I have a clone of UHD 4.7 (Tags: v4.7.0.0) and am trying to build the
default X310_XG FPGA to check if my setup is OK.
I ran the following commands from /uhd/fpga/usrp3/top/x300
source ./setupenv.sh
rfnoc_image_builder -y x310_XG_rfnoc_image_core.yml -t X310_XG
After some time I get t
Hi All,
Is there an example on how to build the rfnoc-example in UHD 4.7 using the
rfnoc_image_builder utility?
Thanks,
Marino
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Thanks for your reply. I resolved it once I updated Vivado with the patch from
Xilinx/AMD
https://support.xilinx.com/s/article/76780?language=en_US
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Further to my last message:
After reading this:
https://lists.ettus.com/empathy/thread/FZYNEWJQYBKFJWC5LASSD5LOL6J765KU?hash=5JXCSAWOZJ6UEOSK3IPXZCIVS277B2SF#5JXCSAWOZJ6UEOSK3IPXZCIVS277B2SF
I tried this:
```
export UHD_FPGA_DIR=~/git/uhd/fpga/
```
```
export RFNOC_OOT=~/git/uhd/host/examples
Hi Martin,
I tried that switch and was a bit worried that. Thanks for confirming it is OK
for the time being.
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Hi All,
I would like to try use the dissector with Wireshark and have run into some
hassle building it, see error below.
thank you,
Marino
```
Scanning dependencies of target rfnoc64
```
```
[ 14%] Building C object epan/rfnoc/CMakeFiles/rfnoc64.dir/plugin.c.o
```
```
[ 28%] Building CXX obj
Just needed to do this:
```
sudo apt install libgnutls28-dev
```
```
sudo apt install libgcrypt-dev
```
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Hi
We have a OOT RFNOC project and have built the UHD framework with DPDK
installed but we don’t use DPDK. Is there any side-effect in doing so? Would
it be better to not have the DPDK libs installed at all?
Thank you,
Marino
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Please ignore my last post, Unfortunately there is no way to delete it.
Basically I was remotely accessing the wrong USRP, the one with the above error
has a hardware issue. This is why the loader is not working.
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Hi
I am having the same problem using UHD 4.7 on a USRP-2974. Note I have also
used the JTAG recovery method to be sure, this works fine.
uhd_usrp_probe loads ok too. But when I use uhd_image_loader then there is a
problem
```
uhd_image_loader --args="type=x300,addr=192.168.40.2"
--fp
Hi
I have a bit of code that finds an OOT module, eg.
auto siggen_blocks = graph->find_blocks___
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Hi Ettus
We are having a real challenge trying to align two identical streams feeding
the ubx160 on a usrp-2974. It is a problem we have had for a long time.
The data entering the axi bus is aligned but at the output it can be misaligned
by 5 to 15ns or so.
Is it possible to completely bypass
Hi Marcus,
Thank you for your quick response.
best regards
M.
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Hi All,
Is there a mechanism to set a timeout when reading or writing registers for a
OOT NOC block?
Thanks,
Marino
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If I am calling poke32 or peek32 without setting the time and ack arguments
(just sending the address and data), where they default to:
```
uhd::time_spec_t time = uhd::time_spec_t::ASAP
```
and
```
bool ack = false
```
Would you expect the timeout exceptions to occur? In
Hi Martin
Thank your for your reply.
This is a software question, related to register peek and poke. For example,
if a register read (via ctrlport_endpoint_impl::peek32) is performed, is there
a chance that the software can block (or get stuck)?
Note: I am using UHD-4.7
kind regards,
Mari
Hi Martin,
If there is any other suggestion for me to try please let me know, I am not
really sure what to do next.
Cheers,
Marino
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Hi Martin,
If it is stuck here should it not timeout (either massive @10s the default @
1s) ?
thanks
Marino
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Hi Martin,
I am not able to provide the test code, likely need to do this via NI/Emmerson
partner contacts.
Thanks for your help so far.
Kind regards
Marino
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Hi David,
At the start where we initialise our siggen block there this snippet of code:
---
```
std::cout << "MB Clock Source: " <<
graph->get_mb_controller(0)->get_clock_source() << std::endl;
```
```
std::cout << "MB Time Source: " <<
graph->get_mb_controller(0)->get_time_source() << std::e
Thanks for your reply.
To answer your last question and give you some context.
The ability to monitor FIFO status would be for debug purpose. The application
we have that is interfacing to a custom RFNOC block via UHD can get are stuck
(randomly over some period of time) and I am trying to fi
Hi Martin,
I don’t fully understand you comment about it not being the block controller.
(bear with as I am not super experienced)
At the moment I have not trapped a timeout exception just yet (see snippet
below). It could well be somewhere else in the application as you say.
---
```
Thank you for your help David.
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Hi Martin
I am still trying to investigate this issue, recreating it is difficult as it
can take long time.
However, on a system that crashed I observed a thread “uhd_ctrl_ep0001”
specifically its CPU utilisation (I have isolated this to use a single CPU and
not share it). Normally it is belo
I would like to know if it is possible to dual boot NI Linux with Ubuntu.
I have tried it but have not been very successful. Ubuntu detects NI Linux
but does not successfully configure the GRUB menu.
Thanks
Marino
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Hi Lukas,
What setting do you have the digital attenuator set to?
Kind regards
Marino
On Mon, 7 Dec 2020 at 02:05, Lukas Haase via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Hi Marcus,
>
> Thanks again!
>
> I did now the following experiment: I connected TX to RX back-to-back with
> 4
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