I am making a custom block which has to start storing data to be read later, in
other words store the data in a FIFO. I am interested in using the RAM provided
by the E320 so I want to take advantage of the axi_ram_fifo code. However, I
don't really understand the control of that block, how can
Hi every one,
When i created a new rfnoc, always the m_in_payload_ready is assigned by
s_out_payload_valid. However, i want to separeted this. I want to get data at a
different rate. To do this I created an FPGA that controls the ready and
validation of s_payload like the m_ready but when I te
Sorry, not FPGA, a FIFO. Now, I have changed that for the axi_fifo to check.
The connections are: Input payload -> Axi_fifo -> Output payload. However, I
don't get the same data at input and output. Also, it seems that the output is
repeated.
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USRP-
