Hello everyone,
I am just starting to use RFNoC and I am a bit confused with hardware
compatibility for RFNoC development.
In order to describe my setup I will list items below:
1. I have NI USRP RIO (equivalent of X310 with integrated GPS module)
2. I am connecting it with PC over
rp-users@lists.ettus.com
> Subject: Re: [USRP-users] NI USRP / PCIe interface and RFNoC FPGA images
>
> On 01/29/2018 07:37 PM, Tarik Kazaz via USRP-users wrote:
>> Hello everyone,
>>
>>
>>
>> I am just starting to use RFNoC and I am a bit confused with har
igE. In order to get the full bandwidth of the X3x0, which
is 2x 200 MS/s on receive, you would need to use both 10 GigE connections.
https://kb.ettus.com/X300/X310#Choosing_a_Host_Interface
Regards,
Derek
On Tue, Jan 30, 2018 at 10:01 AM, Tarik Kazaz via USRP-users
mailto:usrp-users@lists.ettu
to use both 10 GigE connections.
https://kb.ettus.com/X300/X310#Choosing_a_Host_Interface
Regards,
Derek
On Tue, Jan 30, 2018 at 10:01 AM, Tarik Kazaz via USRP-users
mailto:usrp-users@lists.ettus.com>> wrote:
Hello Martin,
I hope I am replying now correctly (I am using reply all to you and m
Hello everyone,
I am considering to synchronize several USRPs Xseries. However, I have only one
device with integrated
GPS disciplined oscillator.
I am wondering whether it is possible to use the device with GPS disciplined
oscillator as a master clock source?
What is the output of REF Out po
Hi All,
I am using USRP X310 with UBX-160MHz. I tried to run RFNoC fosphor demo,
however I am getting errors related to connection of RFNoC:Radio to RFNoC: DDC
and to RFNoC:Window (Source IO size "8" does not match sink IO size "8192"). I
found this discussion on mailing list (from 2016)
http
Hi All,
I am using USRP X310 with UBX-160MHz. I tried to run RFNoC fosphor demo,
however I am getting errors related to connection of RFNoC:Radio to RFNoC: DDC
and to RFNoC:Window (Source IO size "8" does not match sink IO size "8192"). I
found this discussion on mailing list (from 2016)
https
rning and
run the flowgraph.
Regards,
Nate Temple
On Mon, Mar 19, 2018 at 8:59 AM, Tarik Kazaz via USRP-users
mailto:usrp-users@lists.ettus.com>> wrote:
Hi All,
I am using USRP X310 with UBX-160MHz. I tried to run RFNoC fosphor demo,
however I am getting errors related to connection
Dear All,
We are working on prototyping Signal Processing Algorithms for Radar and
localization scenarios (wideband signals).
At the moment we are setting up the testbed for testing our algorithms. We are
interested in the streaming and storing of high data rate
samples full bandwidth of 2x 160
Hi All,
I did further research on issues related to streaming and storing IQ samples
from USRP X310 (with UBX-160) sampling at 200Msps to PC.
The connection between USRP X310 and PC would be over two (2) 10 Gigabit
Ethernet interface.
Based on my calculations writing speed to the memory of PCs
ith fresh values and thus most bits are probably
shorter stored in RAM than one DRAM refresh cycle would be anyway does
probably help physically, too.
Best regards,
Marcus
On Wed, 2018-06-27 at 08:30 +, Tarik Kazaz via USRP-users wrote:
> Hi All,
>
> I did further research on issue
Hi Nives,
It is not clear for me what is your issue. However, based on what you have
wrote I think you have issue with
Implementing and understanding decimation.
Here is short explanation what is decimation. With decimation of digital signal
you are removing some samples
of your signal in order
Hi All,
I am giving up hope of sampling signals of full BW of two UBX-160 cards, and
storing those streams in the PC.
Based on my calculations (one of the previous posts) in order to be able to do
that I would need to write to
memory with the speed of 1.6GBps.
However, now I am interested in sa
benefits if the FPGA DSP could limit the number of samples that
are actually sent to the host, but it is an efficiency gain you likely don't
need.
Regards,
Derek
On Mon, Jul 9, 2018 at 11:01 AM, Tarik Kazaz via USRP-users
mailto:usrp-users@lists.ettus.com>> wrote:
Hi All,
I am giv
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