Hi Derek,
Thank you for the advice and comments. So UHD requires connection of Dual 10GBe interface to single PC. I have experience with FPGA and debugging. However, I did not explore RFNoC FPGA design (I did read few papers about RFNoC). If it really complicated I would like to avoid implementing signal detection there. However, I am still wondering will PC be able to process 400Msps of data in burst mode. Did you guys do similar experiments at ettus? What we want is to test our signal processing algorithm for localization. For that, we transmit wideband signals (of 320MHz, two UBX card are stitched together) from several anchor nodes to the mobile node which we want to localize (this node also has USRP X310 with two UBX cards). While sending signals from 320 MHz from anchor should not cause us issues (as signals are same all the time,so we can store it in USRP itself). I am worried how PC and USRP will behave in case of the receiver (mobile node) as there we need to us PC to store our samples. Kind Regards, Tarik ________________________________ From: Derek Kozel <derek.ko...@ettus.com> Sent: Monday, July 9, 2018 12:37:16 PM To: Tarik Kazaz Cc: usrp-users@lists.ettus.com Subject: Re: [USRP-users] Detecting and sampling short bursts of signals at full sampling rate of USRP X310 for longer period of time Hello Tarik, Just stepping in to respond that UHD does not support splitting the 10 GigE interfaces to two computers. The X310 supports RFNoC which you could use to create an energy detection block which only streams samples back to the computer when your criteria are met. However it is likely simplest for you to do the energy detection on the host computer, streaming the full bandwidth to the computer but then only saving samples long term if your detector identifies a signal of interest. Host coding is almost invariably faster and simpler to debug than FPGA code, though of course there are cases where putting processing in the FPGA is either more efficient or provides unique benefits. In this case you could see some very good efficiency benefits if the FPGA DSP could limit the number of samples that are actually sent to the host, but it is an efficiency gain you likely don't need. Regards, Derek On Mon, Jul 9, 2018 at 11:01 AM, Tarik Kazaz via USRP-users <usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>> wrote: Hi All, I am giving up hope of sampling signals of full BW of two UBX-160 cards, and storing those streams in the PC. Based on my calculations (one of the previous posts) in order to be able to do that I would need to write to memory with the speed of 1.6GBps. However, now I am interested in sampling short bursts of signals with the full bandwidth of USRP x310 (so 2(cards)x2(IQ)x200MSPs) and then storing them into PC memory for the period of 10 minutes. The idea would be to stream bursty signal when the signal is in the air. For this, I would probably need to have some sort of energy detector in the FPGA. The idea would be that energy detector signalizes when the signal is in the air and to trigger streaming samples towards PC. In this way, I would try to lower requirements on the speed of memory write in the PC. Does anyone have experience with doing the same? Previously, I was interested in the possibility to connect single USRP-X310 to two separate PCs over 10GBe interfaces (to split dual 10GBe connection to two PCs with NVMe SSDs). In that way, there would be a possibility to lower down requirements on memory writing speed to 0.8GBps. These memory writing speeds should be supported by modern NVMe SSDs. Probably this is not straightforward to achieve as I did not get too many replies on my previous post. More details about my previous posts are available here https://www.mail-archive.com/usrp-users@lists.ettus.com/msg05579.html. Cheers, Tarik _______________________________________________ USRP-users mailing list USRP-users@lists.ettus.com<mailto:USRP-users@lists.ettus.com> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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