[USRP-users] RFNoC block not fully recognized by UHD 4.0

2020-09-17 Thread Jim Palladino via USRP-users
Hello, I just updated my rfnoc workflow to UHD 4.0 this week. I've gone through the process of creating an RFNoC block, building the corresponding FPGA image, putting it on an E320 (had to upgrade MPM), and seeing the block is present when executing uhd_usrp_probe. The problem is that the block

[USRP-users] Trouble getting custom RFNoC block to work with gnuradio 3.8 / uhd 4.0

2020-09-30 Thread Jim Palladino via USRP-users
Hello, Several weeks ago I went through the tutorial for producing the example "gain" block using rfnoc 3.8 and uhd 3.15. There were some bumps, but I did get that working fine. For the past couple weeks, I've been working with UHD 4.0 and the latest gr-ettus repo. I posted a question a week o

Re: [USRP-users] Trouble getting custom RFNoC block to work with gnuradio 3.8 / uhd 4.0

2020-10-01 Thread Jim Palladino via USRP-users
xample (in-tree would be easiest) to automatically include the DDC and then insert the command line "block-id" optionally after the DDC. - In my testbenches, I have occasionally seend CHDR error messages like you mentioned and it seemed to solve them if I set "s_out_payload_tkeep=1&q

Re: [USRP-users] Trouble getting custom RFNoC block to work with gnuradio 3.8 / uhd 4.0

2020-10-07 Thread Jim Palladino via USRP-users
that you might not need to modify the default example). I don't know a lot about the E320 so I'm not really sure what control you have over the master clock rate (and ultimately the radio output rate). On Thu, Oct 1, 2020 at 11:10 AM Jim Palladino via USRP-users mailto:usrp-

Re: [USRP-users] New mender instructions?

2020-10-09 Thread Jim Palladino via USRP-users
Hi Rob, Per (https://files.ettus.com/manual/page_usrp_e3xx.html#e3xx_rasm_mender) I used the following on an E320: mender install /home/root/usrp_e320_fs.mender I'm pretty sure I needed to add a force flag to it as well. Jim From: USRP-users on behalf of Rob

[USRP-users] Adding Xilinx IP to custom RFNoC block

2020-10-15 Thread Jim Palladino via USRP-users
Hello, I'm trying to add a Xilinx DDS to a custom RFNoC block (using UHD 4.0 and associated gr-ettus repo). To do this, I started building the FPGA image using the GUI option, stopped the build shortly after Vivado opened, and saved a Vivado Project. Then, in Vivado I configured/added a Xilinx

Re: [USRP-users] Adding Xilinx IP to custom RFNoC block

2020-10-15 Thread Jim Palladino via USRP-users
v:14] ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details [00:04:25] Current task: Synthesis +++ Current Phase: Starting [00:04:26] Current task: Synthesis +++ Current Phase: Finished [00:04:26] Process terminated. Status: Failure Thanks, Jim

[USRP-users] E320 Autoboot

2020-10-27 Thread Jim Palladino via USRP-users
Hello, I have an E320 that I'm trying to get to auto-boot when power is applied (so the button doesn't need pushed). I followed instructions here (https://kb.ettus.com/E320_Getting_Started_Guide#Enable_Auto_Booting) to set the autoboot flag, but it isn't working (not automatically booting when

[USRP-users] E320 SFP speed/duplex question

2020-12-09 Thread Jim Palladino via USRP-users
Hello, I just setup an E320 with a 1Gbps SFP. I've updated the filesystem, FPGA load (with the "1G" build"), etc and am using UHD 4.0. uhd_usrp_probe seems happy, and I created a gnuradio flowgraph and streamed samples ok. I did not test throughput, though. What concerns me is that when I conne

Re: [USRP-users] E320 SFP speed/duplex question

2020-12-09 Thread Jim Palladino via USRP-users
SRP is working as desired & that's the bottom line here hopefully! - MLD On Wed, Dec 9, 2020 at 9:44 AM Jim Palladino via USRP-users mailto:usrp-users@lists.ettus.com>> wrote: Hello, I just setup an E320 with a 1Gbps SFP. I've updated the filesystem, FPGA load (with the "1

Re: [USRP-users] E320 SFP speed/duplex question

2020-12-09 Thread Jim Palladino via USRP-users
GA image. Once configured on both ends, if data transport is working then, if Linux / ifconfig / ethtool still shows 10 Gb link speed then, yes, something is off with those tools -- but, clearly the USRP is working as desired & that's the bottom line here hopefully! - MLD On Wed, Dec 9

Re: [USRP-users] E320 SFP speed/duplex question

2020-12-10 Thread Jim Palladino via USRP-users
From: USRP-users on behalf of Jim Palladino via USRP-users Sent: Wednesday, December 9, 2020 2:03 PM To: Michael Dickens Cc: usrp-users@lists.ettus.com Subject: Re: [USRP-users] E320 SFP speed/duplex question Thanks again for the response and information. I'm s

Re: [USRP-users] Opening Vivado GUI during FPGA image build

2021-02-09 Thread Jim Palladino via USRP-users
It's been a while since I did this, but I had issues bringing up the gui as well. Here is a copy/paste of some notes I wrote for myself: * Edit the file "$PREFIX/bin/rfnoc_image_builder". * Find the line "gui=args.GUI" and change it to "GUI=args.GUI" and save it. * Next, edit "$PREFI

Re: [USRP-users] OTT Gain Block stopping samples flowing from RFNoC Digital Down Converter

2021-02-17 Thread Jim Palladino via USRP-users
Hi Mark, I'm not sure if this is your problem, but I had a similar issue. After some debugging, I found that for some reason, with the OOT RFNoC Block inserted, the total size of the CHDR packet plus the Ethernet header that gets added on in the FPGA would slightly exceed the MTU size (mine was

Re: [USRP-users] OTT Gain Block stopping samples flowing from RFNoC Digital Down Converter

2021-02-17 Thread Jim Palladino via USRP-users
Hi Mark, Yes, that is how I set spp in my flowgraph. I don't think this is the issue, but The E320 Getting Started Guide says: * Streaming via SFP0 at 1 Gb rates requires a MTU of 1500 * Streaming via SFP0 at 10 Gb rates requires a MTU of 8000 That is why I was using an MTU of 8000. May