Hello Arjan,
This is a known issue and a fix for it should be released in the next few
weeks on the UHD master branch. Another option is to revert to UHD 3.15
until the fix is released.
Jonathon
On Sat, May 29, 2021 at 11:08 AM wrote:
> Hi all, I'm trying to build an RFNoC graph (x300 with a T
Hi Aneesh,
Thanks for your comment. I used a Intel(R) Core(TM) i7-8850H CPU for the
B-series experiment (which is somewhat weaker than the "AMD Ryzen 9
3900X 12-Core Processor" I used with the X310s, but the sampling rate
was only 1MHz in both cases, so it should be fine). The software is
bas
Great info and thanks for the use case. Makes sense for the precision you need
for your situation.
Since really it's just IO, basic driver calls, and instrumentation and your
specs support all of that (assuming no weird nuances / I say this to cover
myself ha), your sample methods seems great.
Different synthesizers have different phase noise properties.
I suspect that if so the same test at lower frequencies on the B2xx things will
improve.
Also the external-clock PLL in the B205 is much poorer than on the other family
members—B200 and B210.
Sent from my iPhone
> On Jun 3, 2021
You're right Marcus, 0.9GHz seems to be better indeed (see image). Also
thanks for the input on the B205 PLL.
May I ask in what way phase noise can affect the signal's frequency?
According to an NI webpage [1], it "deals with very short time scales
and produces effects that look more like unwa
