Dear all,
On USRP2, there was a concept of user registers,
i.e. memory allocated in FPGA for the user, using user_settings,
that the user can set in C++, using the UHD C++ API set_user_register.
I am trying to reproduce such behaviour on X300 using UHD 3.9 LTS (i.e
pre-RFNOC).
I am solely intere
On Tue, Feb 16, 2021 at 10:15 AM Mike via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Any ideas?
Try changing the clock domain connection to your FFT block to this:
- { srcblk: _device_, srcport: rfnoc_chdr,dstblk: fft0, dstport:ce
}
Does that allow rfnoc_image_builder to complet
I'm working with an E320 using UHD 4.0.
I've been working through the video "RFNoC 4 Workshop - GRCon 2020" to install
my own custom signal processing block into the RFNoC on the FPGA.
I've also been following the guide AN-121 "Debugging FPGA images" and have
added Chip Scope probes to the payl
Hi Mark,
I'm not sure if this is your problem, but I had a similar issue. After some
debugging, I found that for some reason, with the OOT RFNoC Block inserted, the
total size of the CHDR packet plus the Ethernet header that gets added on in
the FPGA would slightly exceed the MTU size (mine was
Thanks Jim,
I'm using eth0 on the E320 which is set with an MTU of 1500 and this seems to
be the maximum. If I try to set it to 1501 it says that's greater than the
maximum allowed.
I've now switched to using the SFP+ port rather than eth0 which has an MTU of
9000, but this hasn't had any effe
Dear Mr. Müller,
Thanks for the script and of course fast response!
We are running in loopback mode (tx to rx), and we have tried to change the tx
and rx gain (attenuation) pairs while keeping a constant link budget in the
loop. We had inconsistent results in terms of ADC dynamic (bits) utili
Hi Mark,
Yes, that is how I set spp in my flowgraph. I don't think this is the issue,
but The E320 Getting Started Guide says:
* Streaming via SFP0 at 1 Gb rates requires a MTU of 1500
* Streaming via SFP0 at 10 Gb rates requires a MTU of 8000
That is why I was using an MTU of 8000. May
On 17/02/21 15:35, Mark D via USRP-users wrote:
> I'm working with an E320 using UHD 4.0.
> [...]
> However if I reconfigure the GNU radio to "RFNoC RX Radio"->"RFNoC Digital
> Down Converter"->"RFNoC Gain"->"RFNoC Rx Streamer"->"QT GUI Time Sink" the
> system no longer works.
>
> The Time Sink
Hi Cédric,
not that hard: you need an instance of settings_register, which you connect to
the
appropriate settings bus.
It's probably easiest if you look through the FPGA code matching your version
of UHD
(check out the UHD source repository, `git checkout` the tag that corresponds
to the UHD
Could this be another case of the "issue_stream_cmd" never making it from
the streamer to the Rx radio? Cédric, didn't we find that if you don't
have a custom block controller, the stream cmd does not propagate as expect
to the Radio and thus you get a recv() timeout?
Rob
On Wed, Feb 17, 2021 at
I have UHD 3.15 successfully cross-compiled for E310 on Ubuntu 18.04
host. Now trying to cross-compile GnuRadio 3.7. My cmake is:
cmake
-DCMAKE_TOOLCHAIN_FILE=~/rfnoc/src/gnuradio/cmake/Toolchains/oe-sdk_cross.cmake
-DENABLE_DOXYGEN=OFF -DCMAKE_INSTALL_PREFIX=/usr
-DCMAKE_ASM_COMPILER_ARG1:STRING="
This should probably be cross posted to the discuss-gnuradio mailing list just
to get some more gnuradio-specific eyes on it.
Sent from my iPhone
> On Feb 17, 2021, at 2:26 PM, Dennis Trask via USRP-users
> wrote:
>
> I have UHD 3.15 successfully cross-compiled for E310 on Ubuntu 18.04 host
12 matches
Mail list logo
