Hi Marcus,
My goal is to get NTP daemon running on N300 synced with GPSDO and PPS. Could
it be that the GPSDO time is internally latched with the PPS line? If this is
the case then I guess that it would not be necessary to read the PPS.
I have seen the "Device Synchronization" section and "syn
Hi Pat,
Are you using fiber or copper to connect? If you are using fiber, it seems
to me it could work with a three QSFP optical transceivers and three MTP/LC
breakout fibers that you would connect via couplers such that Host Lanes 0
and 1 go to the first N321 Lanes 0 and 1 while the Host Lanes 2
I should add that when I said "I have not done this", I meant with N321s in
this proposed configuration. However, I am presently using an XL710 (QDA1)
with a QSFP+ optical transceiver and MTP/LC breakout fiber to connect to
two N310s (using SFP+ optical transceivers). I have done this both with
s
Hi Pat - Thanks for your sleuthing and info from Intel on how the XL710
Intel NIC allocates lanes when in 2x2x10 mode. This is certainly an issue
with what the N321 expects. It would be desirable if the Intel NIC
configuration utility allowed one to select which lanes to use, and/or if
we could pro
On 02/04/2021 03:30 AM, Puertas Blanco, Roberto via USRP-users wrote:
Hi Marcus,
My goal is to get NTP daemon running on N300 synced with GPSDO and
PPS. Could it be that the GPSDO time is internally latched with the
PPS line? If this is the case then I guess that it would not be
necessary to
Good info. Thanks. I am attempting to burn a new image to the SD card.
I downloaded
https://files.ettus.com/binaries/cache/e3xx/meta-ettus-v3.14.1.1/e3xx_e320_sdimg_default-v3.14.1.1.zip
which contains usrp_e320_fs.sdimg. Will this work to boot my e310?
Dennis
-
Dear Sir or Madam,
I would like to use one of the available FPGA blocks from Ettus – such as FIR
filter -- to customize my FPGA image, and add the corresponding control driver
for C++ application and Gnuradio. However, after creating newmod with
rfnocmodtool, I have tried to add fir filter bloc
On Thu, Feb 4, 2021 at 1:15 PM Askar, Ramez via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Dear Sir or Madam,
>
>
>
> I would like to use one of the available FPGA blocks from Ettus – such as
> FIR filter -- to customize my FPGA image, and add the corresponding control
> driver for C++ appl
On 02/04/2021 12:12 PM, dtra...@tampabay.rr.com wrote:
Good info. Thanks. I am attempting to burn a new image to the SD card.
I
downloaded https://files.ettus.com/binaries/cache/e3xx/meta-ettus-v3.14.1.1/e3xx_e320_sdimg_default-v3.14.1.1.zip
which contains usrp_e320_fs.sdimg. Will this work to
Hi Ramez,
I'd like to recommend a thorough viewing of the excellent RFNoC 4
Workshop video that Jonathon Pendlum and Neel Pandeya from Ettus
Research put together for GRCon 2020, which is available on YouTube at
https://www.youtube.com/watch?v=M9ntwQie9vs. This should walk you
through the process
I can help with that. It doesn't. :-) The serial port just displays
some garbage characters at bootup.
I think I've got this figured out. I went back through the
instructions, but grabbed the v3.15.0.0 tag for UHD, instead. Then, I
discovered that I could get an sdimg and an SDK for that version us
11 matches
Mail list logo
