Hi,
i'm trying to simulate a block where i'm using cmul. in order to have that
compiled in i am including the following in my Makefile under rfnoc/fpga in
my OOT directory:
include $(BASE_DIR)/../lib/ip/Makefile.inc
SIM_SRCS = $(abspath rfnoc_block_demod_tb.sv) \
$(LIB_IP_COMPLEX_MULTIPLIER_OUTS)
I was setting samp_rate to 1 msps and observed the same situation. In
addition, in the example fosphor samp_rate = 56 msps and no errors
occur.
сб, 21 нояб. 2020 г. в 05:12, Marcus D Leech :
> There’s no way the fpga to ARM channel can support those data rates.
> Lower your sample rate to 5msps
Marcus,
I tried it without timed commands last night. It was landing on the
same frequencies as it did with timed commands i.e. didn't fix that
problem.
Dustin
On Wed, 2020-11-18 at 20:05 -0500, Marcus D. Leech wrote:
> On 11/18/2020 07:34 PM, Dustin Widmann wrote:
> > On Wed, 2020-11-18 at 18:
On 11/21/2020 08:28 AM, Dustin Widmann wrote:
Marcus,
I tried it without timed commands last night. It was landing on the
same frequencies as it did with timed commands i.e. didn't fix that
problem.
Dustin
OK, thanks for doing the test.
I wonder if you have a precise signal generator so you c
On 11/21/2020 06:53 AM, Ivan Zahartchuk wrote:
I was setting samp_rate to 1 msps and observed the same situation. In addition,
in the example fosphor samp_rate = 56 msps and no errors occur.
If you replace the ZMQ blocks with NULL SINK blocks, do the overruns go
away?
сб, 21 нояб. 2020 г.
Hi Ivan,
The Fosphor block averages and then significantly decimates the FFT output.
With the default settings, it has an output data rate comparable to a 500
kSPS stream. The Fosphor example is also only one channel.
I would suggest starting at a rate of 100 kSPS and increasing from there.
The E
Hi Dario,
Unfortunately, Vivado's xsim simulator sometimes crashes when it runs into
syntax and elaboration errors. Make sure you don't have issues like signals
with multiple drivers, undriven signals, missing reset logic, typos, etc.
Note that these issues may be in code that is/seems unrelated t
Hi,
i am trying to debug my block and to do so i ran
GUI=1 make n310_rfnoc_image_core
this brings up vivado and allows me to synthesize the design and setup ILA.
when i try fitting and generating bitstream i get the following error:
[DRC PDRC-29] MMCM_adv_ClkFrequency_clkin1: The calculated freq
