[USRP-users] B210: LO and noise issues

Hi, from the AD9361 data sheet I learn that the USRP B210 has two seperates LOs, one for TX and one for RX. On the other hand, the two TX and RX channels share one LO, respectively. I wonder if there is an operation mode where TX and RX use the SAME LO, or some trick to achieve this. Probabl

Re: [USRP-users] B210: LO and noise issues

Hi, > I wonder if there is an operation mode where TX and RX use the SAME LO, or > some trick to achieve this. Probably not? The AD9361 itself allows for external LO injection ( RX_EXT_LO_IN , TX_EXT_LO_IN ), but that's not broken out in anyway on a B2xx. You'd need serious rework skill to get t

Re: [USRP-users] transmitting on two channels with replay block

Thank you Rob for this comment. But I am not sure if I understand you correctly. Do you want to say, that it is IMPOSSIBLE to stream TX two different waveforms synchronized on the 2 channels of the x310 with the full bandwidth of 200MS/s on each channel? That is what I am trying the last 6 month

Re: [USRP-users] Default RFNoC image for N310 does not compile

Hi Nate, the image does compile now with the patch. However there still seems to be s.th. wrong on the host side. When running uhd_usrp_probe, it fails when it reaches the split_stream block: [INFO] [0/SplitStream_0] Initializing block control (NOC ID: 0x5757) [ERROR] [MPMD] Failu

[USRP-users] UHD Versions for N310

For an X310, I am currently using: $ uhd_config_info --version UHD 4.0.0.rfnoc-devel-702-geec24d7b I would like to update my N310 to the same version as my X310 so I can use it in Network mode like the X310 without having multiple versions of UHD. Since I've had some version configuration iss

Re: [USRP-users] transmitting on two channels with replay block

I do not think it is possible using the stock FPGA image. However, I can think of a couple of possibilities: - On the N310, Ettus includes 4 FIFO blocks (rather than the DmaFIFO which used the off-FPGA RAM for memory), to provide capability for 4x125 MS/s streaming. Perhaps if you built

Re: [USRP-users] transmitting on two channels with replay block

Hi Thomas, One option instead of using the Replay block could be to stream 2x 200e6 from your host. On the X310, this requires using a SRAM image and DPDK. DPDK support was added with UHD 3.14.1.0 for the X310, I'd suggest to use 3.14.1.1 at this time though. Some links on DPDK: https://www.dpd

Re: [USRP-users] B210: LO and noise issues

Thanks for the suggestion. I have tried this and it turns out, the noise is mostly phase noise. Simply by subtracting the phase of the second channel from the first, I can reduce the noise already by about 20 dB. May be, more reduction is possible by some sophisticated mathematics. Best rega

Re: [USRP-users] transmitting on two channels with replay block

Just to pile on yet another fpga option: Nick Foster and others here have experimented with custom rfnoc blocks that have two connections to the rfnoc crossbar rather than just one... Hypothetically, a custom replay block with a split stream and two crossbar connections (one for each output) could

Re: [USRP-users] transmitting on two channels with replay block

On Wed, Dec 11, 2019 at 9:33 AM Nate Temple wrote: > Hi Thomas, > > You will need to apply these changes below to the > fpga-src/usrp3/top/x300/rfnoc_ce_default_inst_x310.v file. This will add > additional SRAM FIFOs, which is basically what the "XGS" / SRAM image is. > Make sure to start with th

Re: [USRP-users] Noise vs Sample rate

Hello Thibaud, Think this in the frequency domain. A typical decimator 1. applies a low-pass filter to the incoming samples, and then 2. downsamples the data by extracting every n th sample. The low-pass filter does not only filter out non-desired signals, but also filters out noise. So, you m