In brief, (since the CORDIC algorithm is a simple and fun one to simulate
standalone and look at the functions generated as analog waveforms)
The zi input (fed from the DDC/DUC phase accumulator) represents an angle as a
fraction of 2*Pi.
The symmetry of the sin/cos functions is exploited so that
Dear member of the Ettus mailing list,
particularly those of you actually expert in RFNOC.
We have started recently to try to use the rfnoc_devel branch of UHD and of the
FPGA source code in order to implement a project where we want to transfer part
of the processing on the FPGA. In a prelimina
Dan,
I've been testing and I was able to reproduce something that might be your
issue. I'm still testing, but if you want to try the following change, it
might fix your issue. Simply delete this line and rebuild the FPGA:
https://github.com/EttusResearch/fpga/blob/4f25ed1b4129c94677b66540894a03a
Hi all,
We are trying to send 4 synchronous signals from the 4 Tx ports of the N310.
We are using UHD 3.13.1.0 RC1 under Ubuntu.
Central Freq = 1575.42 GHz and 1227.6 MHz
Master Clock rate = 153.6 MHz
We would expect to have less than 3ns offset between all TX ports of the
N310, like we do with t
On 11/07/2018 08:53 PM, Serge Malo via USRP-users wrote:
Hi all,
We are trying to send 4 synchronous signals from the 4 Tx ports of the
N310.
We are using UHD 3.13.1.0 RC1 under Ubuntu.
Central Freq = 1575.42 GHz and 1227.6 MHz
Master Clock rate = 153.6 MHz
We would expect to have less than 3
Yes:
We only use one streamer for all RF outputs, and send time_spec with each
call to the streamer's send method.
We reset the internal time with set_time_unkown_pps(0), and program the
first samples to be streamed at a time of 0.800s.
It is basically the same code we used on the X300/X310.
Thank
On 11/07/2018 09:31 PM, Serge Malo wrote:
Yes:
We only use one streamer for all RF outputs, and send time_spec with
each call to the streamer's send method.
We reset the internal time with set_time_unkown_pps(0), and program
the first samples to be streamed at a time of 0.800s.
It is basically
Hi Martin,
Thanks for the detailed feedback! I'll not worry about FPGA loading
timeouts. I'm also not terribly concerned about local FPGA loading either,
though it is perhaps worth noting if the uhd_image_loader and
uhd_images_downloader should default to python3 on the n3xx PS.
> It is not. UHD/
