Hello Alice,
I'm myself not aware of an existing project (maybe I just forget, though) which
puts a microblaze into an rfnoc block, but:
Why not? You can put anything that you can instantiate in verilog into a block;
I'd presume you might want to add a bus-independent clock to drive your
proces
Go Harfan,
It is internally assumed that a streamer during its life time has a fixed
number of streams. What sampling rate are we talking about? Is continuity for
the other channels a concern? What is the time scale we're switching channels
on an off?
Best regards,
Marcus
On 16 May 2018 13:02:
Hi Keith,
in principle, you could continue using the multi_usrp in **one** of the
processes. The real problem stems from the question of who inherits the sockets
(in the case of network USRPs), the USB handles, or kernel ring buffer handles.
In the end, only one process might react to packets co
Hi Miguel,
I'm definitely not an expert on windows software building, but "the libuhd
environment" actually sounds like it is what you want to build. You probably
shouldn't try to link your build of libuhd against our build.
Best regards,
Marcus
On 14 May 2018 06:16:12 GMT+02:00, Miguel P via
Hi Risa,
the chances of us getting mad are extremely slim :)
I presume you've already made progress in this; if not: what line exactly does
your debugger say your segmentation fault happens? If you haven't worked with a
debugger before (in your case, probably gdb), it's a skill that pays to le
Hi,
I'm comparing two cases that, in theory (at least in my understanding
of things), should yield the same result but don't :)
1) I'm sending data to the USRP at sample_rate N with
master_clock_rate N and the ADI has FIR 4x, HB 2x,2x,2x
2) I'm sending data to the USRP at sample_rate N with
mast
Hi Marcus,
Thank you for your reply.
Currently I have created two streamer with first streamer goes to channel 0
and second streamer goes to channel 2. The sampling rate is same for both
channel. I am successfully controlling the stream from channel 0 to channel
2. However when i try to change back
Hi all,
creating RFNoC-OOT without Xilinx IP blocks works fine, but somehow I
struggle with adding the Xilinx IP xcix files from Vivado to the RFNoC-OOT.
The rfnocmodtool creates a Makefile.srcs (manually modifying this file is
not recommended according to the tutorial). In contrast, some oth
Hi Marcus,
Thank you very much for your previous reply.
Yeah i have progressed very far from my previous question. However, i still
have a problem when i try to run the application using 2 USRP, I saw only 1
light indicator in TX/RX is ON which i believe only one USRP is sending the
data (On RX sid
Hello Yichao Yu:
What is your status on this issue?
If this issue is still outstanding for you, could you please share your
program with us (you can email it to us directly and privately, if you
prefer), so we can see exactly what you're doing.
--Neel Pandeya
On 19 April 2018 at 10:28, Yich
On 05/16/2018 07:02 AM, harfan ryanu via USRP-users wrote:
Hi all,
Currently I am developing an application with multi usrp using two
X310. My current configuration is using all 4 channel in usrp with all
subdev enabled (A:0 B:0), both feed by an external clock. However I am
curious if we have
We don't have a more-granular usage report for FPGA utilization. But you
can experiment by removing blocks that you don't need, and seeing how many
resources free up as a result.
What is the error that you're seeing? Which version of Vivado are you
using? Are you using the rfnoc-devel branch, or a
On 05/19/2018 12:13 PM, harfan ryanu wrote:
Hi Marcus,
Thank you for your respond,,
That is one of the solution i am thinking right now, but to be able to
send zero and turn the gain, i believe i have to use multi usrp object
using only one stream to send to both channel right?
Yes.
However i
Hi Marcus,
Thank you for your respond,
I just realize it seems somebody in the mail list has the same exact
problem with me, but i check noone has answered to the problem.
I have tried to run
./benchmark_rate --tx_rate "1e6" --args "addr0=192.168.40.2,addr1=192.168.50.2"
--channels "0,2" --ref "ext
> What is your status on this issue?
No progress.
> If this issue is still outstanding for you, could you please share your
> program with us (you can email it to us directly and privately, if you
> prefer), so we can see exactly what you're doing.
I believe the only part of the code that's rele
Hello Donna:
In order to achieve a latency less than 10us, you would have to do
processing in the FPGA, using the RFNoC framework. You won't be able to
achieve such a low latency passing samples between the host computer and
the radio.
Regarding streaming rates, have you set read and write socket
Hello Eugene:
I would not suggest modifying the PCIe transfer block sizes. Although the
PCIe bus might be able to achieve latencies of 10 us, there is additional
latency introduced by UHD and the FPGA. In order to achieve a latency less
than 10us, you would have to do processing in the FPGA, using
On 05/19/2018 12:47 PM, harfan ryanu wrote:
Hi Marcus,
Thank you for your respond,
I just realize it seems somebody in the mail list has the same exact
problem with me, but i check noone has answered to the problem.
I have tried to run
./benchmark_rate --tx_rate "1e6" --args
"addr0=192.168.40.
That’s strange, by default the analog filters should be being configured from
the master_clock_rate to have optimal bandwidth for the master_clock_rate on
the assumption your signal uses the bulk of that bandwidth.
UHD version?
> On May 19, 2018, at 2:37 AM, Sylvain Munaut via USRP-users
> wro
Hello LJ Eads:
There are some tutorials that will help you get started with GNU Radio.
https://kb.ettus.com/Suggested_Videos
The UHD USRP Source and UHD USRP Sink blocks in GNU Radio represent your
X300/X310 radio. The source block is for receiving samples, and the sink
block is for transmitting
Hi,
> That’s strange, by default the analog filters should be being configured from
> the master_clock_rate to have optimal bandwidth for the master_clock_rate on
> the assumption your signal uses the bulk of that bandwidth.
That's what I would have thought. Maybe I'm just probing it too early
Hi everyone,
I've got a problem, when try to build E310_sg3.bit:
ERROR: [Place 30-487] The packing of instances into the device could not be
obeyed. There are a total of 13300 slices in the pblock, of which 7850
slices are available, however, the unplaced instances require 9752 slices.
Please ana
Hello Emanuel:
Could you please post the error message from the console?
Does this error persist in UHD 3.11.1.0?
--Neel Pandeya
On 4 May 2018 at 06:51, Marcus D. Leech via USRP-users <
usrp-users@lists.ettus.com> wrote:
> On 05/04/2018 01:45 AM, Emanuel via USRP-users wrote:
>
> Hi,
>
>
>
Or actually it might just be that the usrp_dev->get_rx_bandwidth()
call doesn't return what's really programmed.
Looking at _setup_rates, the var _baseband_bw is setup there.
In case (1) I have rate=N and divfactor=32 (as I mentionned in the
first mail, I force FIR 4x interp here) and _baseband_b
There's a map option in ise that will give a very detailed listing if the
resource usage of every block in your design hierarchy. I'm sure there's
something similar for vivado.
I can't remember the name of it, but I'm sure you can find it if you search
around a little.
Regards,
William
On Sat,
Hello Rob:
This capability is not supported with the multi_usrp API on the X300, X310,
N310.
It was supported on the N200/N210.
https://files.ettus.com/manual/page_usrp2.html#usrp2_altstream
However, this capability is supported for the X300, X310, N310 using the
RFNoC API.
--Neel Pandeya
40
Hello Jong:
I think Robin answered this in a separate thread with you, so I'm just
responding to conclude this thread.
The behavior that you describe is a result of a corrupted bit in the AVR
EEPROM firmware that results in the power-on sequence requiring the power
button to be pushed. This corru
Hi Marcus,
I have tried setting the tx_subdev "A:0 B:0 A:0 B:0" probably you mean only
"A:0 B:0" since it produce another error saying input port already
connected. I have tried another several benchmark configuration as follow:
1. ./benchmark_rate --tx_rate "1e6" --args "addr=192.168.40.2" --tx_su
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