Le 05/04/2018 à 16:29, Marcus D. Leech via USRP-users a écrit :
> On 04/05/2018 04:55 AM, Matis Alun via USRP-users wrote:
>>
>> Hi usrp users,
>>
>> I experienced some problem using my X300 + TwinRx over 1 Gb/s link.
>>
>> The following code example shows that after the iteration number 253, the
Hi all, Marcus,
Thanks for the answer, it was really useful. Now, I am trying to generate
the 10Mhz signal using a vector signal generator, but the signal is nor
really pure because the signal generator bandwidth is only 60MHz. Also, the
Vpp of the signal is 1.4 V, is it correct?
If someone can s
On 04/06/2018 08:29 AM, ALEJANDRO BLANCO PIZARRO wrote:
Hi all, Marcus,
Thanks for the answer, it was really useful. Now, I am trying to
generate the 10Mhz signal using a vector signal generator, but the
signal is nor really pure because the signal generator bandwidth is
only 60MHz. Also, the
Hi Marcus,
Thanks a lot! What GPSDO do you recommend? We need to buy one.
Best regards,
Alejandro
2018-04-06 16:00 GMT+02:00 Marcus D. Leech :
> On 04/06/2018 08:29 AM, ALEJANDRO BLANCO PIZARRO wrote:
>
> Hi all, Marcus,
>
> Thanks for the answer, it was really useful. Now, I am trying to gener
On 04/06/2018 10:16 AM, ALEJANDRO BLANCO PIZARRO wrote:
Hi Marcus,
Thanks a lot! What GPSDO do you recommend? We need to buy one.
Best regards,
Alejandro
Most Ettus customers with more than a single USRP tend to use the
Octoclock-G:
https://www.ettus.com/product/details/OctoClock-G
2018-
Hi,
The rfnoc-devel branch has now been updated to include fixes and requires
Vivado 2017.4. I’ve always created the development environment with PyBOMBS
and it seems as though this always pulls the latest version of UHD from the
GitHub repository. Is there any way to pull the previous version o
Thanks for everyone’s assistance.
I did not get a chance until now to update the situation…
Basically, this is what I did..
I did not look into the screen comment btw….
1) When connected to the SDR via Ethernet cable, at the terminal type –
nohup python namOfFile.py &
2) This will
Making a hardware DDS to generate a chirp in the FPGA is easy, extremely so if
you reuse the Ettus code that interfaces the B210 to AD3961 with correct timing.
What is very hard in what you propose, is controlling the AD9361 from within
the FPGA without an external host. There is a *lot* of confi
Hi,
Are there any examples for using the N310 with external LO? I have gotten
some strange results (strange spectral mirror-ing) when using as just a 4
channel receiver. I am using the "args" argument to set rx_lo_source, but
my code is setting the individual channel frequencies as I do for other
On 04/06/2018 05:14 PM, Rob Kossler via USRP-users wrote:
Hi,
Are there any examples for using the N310 with external LO? I have
gotten some strange results (strange spectral mirror-ing) when using
as just a 4 channel receiver. I am using the "args" argument to set
rx_lo_source, but my code
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