[USRP-users] X310 - Vivado mig segfaults

I have Cygwin64 setup in Windows 10 Vivado 15.4.2 installed and licensed. source setupenv.sh --vivado-path=/cygdrive/c/Xilinx/Vivado/ Setting up a 64-bit FPGA build environment for the USRP-X3x0... - Vivado: Found (/cygdrive/c/Xilinx/Vivado//2015.4/bin) - Vivado HLS: Found (/cygdrive/c/Xilinx/Viva

[USRP-users] NI USRP / PCIe interface and RFNoC FPGA images

Hello everyone, I am just starting to use RFNoC and I am a bit confused with hardware compatibility for RFNoC development. In order to describe my setup I will list items below: 1. I have NI USRP RIO (equivalent of X310 with integrated GPS module) 2. I am connecting it with PC over

Re: [USRP-users] NI USRP / PCIe interface and RFNoC FPGA images

On 01/29/2018 07:37 PM, Tarik Kazaz via USRP-users wrote: > Hello everyone, > >   > > I am just starting to use RFNoC and I am a bit confused with hardware > compatibility for RFNoC development. > > In order to describe my setup I will list items below: > >   > > 1.   I have NI USRP RIO (e

Re: [USRP-users] X310 - Vivado mig segfaults

On 01/26/2018 03:49 PM, Martin K via USRP-users wrote: > I have Cygwin64 setup in Windows 10 > Vivado 15.4.2 installed and licensed. > > [...] > Some web searching shows that other people have had trouble with the mig > failing - on both Windows and Linux, but obviously it works for you > guys.  I

Re: [USRP-users] X310 - Vivado mig segfaults

I did some more searching and I found this github issue with a workaround: https://github.com/EttusResearch/uhd/issues/103 (begin quote): I hit the same ddr3_32bit build error on Windows: [IP_Flow 19-3475] Tcl error in ::ipgui_ddr3_32bit::updateAllModelParams procedure for IP 'ddr3_32bit'. Loadi

Re: [USRP-users] NI USRP / PCIe interface and RFNoC FPGA images

Tarik, please remember to keep responses on the mailing list, lest they get lost. Yeah, just add fpga=/path/to/image.lvbitx to your device args. -- M On 01/29/2018 09:56 PM, Tarik Kazaz wrote: > Hello Martin, > > Could you provide me more detailed instruction, how to disable PCIe to reload >

Re: [USRP-users] RFNoC: Synthesizing a block containing modules from uhd-fpga

Hi Adam, Can you post your testbench makefile? Jonathon On Jan 10, 2018 5:07 PM, "Adam Parower via USRP-users" < usrp-users@lists.ettus.com> wrote: > Hello everyone, > > > I am trying to create a custom RFNoC block that is similar to the built-in > DUC block. As such, it depends on the cordic_t

[USRP-users] Installing Python Modules into E310

Is there a specific method/process to install external modules into the E310? For example, "python bit-array". We would need this module installed to run a .grc file using GNUradio directly on the E310. I have tired installing bitarray directly onto the radio using 'python setup.py install' but was

Re: [USRP-users] x310 simulating RFNoC block with Xilinx IP

Hi Tien, Run 'make xsim' in the same directory as the testbench. Jonathon On Jan 22, 2018 12:52 PM, "Dang tien Vo-Huu via USRP-users" < usrp-users@lists.ettus.com> wrote: Hi EJ, It works! Now I am able to simulate the custom block with IP in both cases. Just another small question, can we simul

Re: [USRP-users] RFNoC Block with two inputs and one output.

Hi Mark, Are you getting a specific error message in GRC? You'll need to post more details for someone to help you. Jonathon On Wed, Dec 13, 2017 at 4:46 AM, Mark Luscombe via USRP-users wrote: > Hi all, > > My next question ;-) > > I want to create a RFNoC Block with two SC16 inputs and one SC