Thank you Marcus for your answer. And happy new year!
As this FIFO induces constraints in the timing of TX and RX parts, are there
plans to modify it by, for example, using two FIFO (TX and RX parts but what
about other requests...) or chained list allowing insertion (may be not easy in
hardwar
Hello all,
I am trying to design an RFNoC block using Vivado 2015.4, but I keep running
into synthesis and implementation critical warnings.
Can you explain to me step by step how to instantiate a working rfnoc block
WITHOUT using gnuradio? It seems that most information I am finding online
The use of Gnuradio will not affect the FPGA design at all. If you supply
the errors you're seeing we might be able to help further.
Nick
On Tue, Jan 2, 2018 at 8:57 AM Adam Kurisko via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Hello all,
>
>
> I am trying to design an RFNoC block using
Hi Nick,
Thank you for your fast response.
I am receiving the following errors:
Synthesis
[Synth 8-4442] BlackBox module inst_axi_interconnect has unconnected pin
s_axi_awprot[2]
[Synth 8-4442] BlackBox module inst_axi_interconnect has unconnected pin
s_axi_awprot[1]
[Synth 8-4442] BlackBox
That all looks ok to me. Does it successfully generate a bitstream?
There will virtually always be warnings, even some "critical" ones, in any
sufficiently complex FPGA project.
Nick
On Tue, Jan 2, 2018, 9:26 AM Adam Kurisko wrote:
> Hi Nick,
>
>
> Thank you for your fast response.
>
>
> I am
Hi Marcus,
1. In the previous version (3.10.002) it does recognize the
daughterboard in slot A, I just don't have a daughterboard populated in
slot B. I am able use it in a regular fashion (TX/RX).
2. I believe it likely to be what you said about the issues with the
EEPROM. Is there any refe
Nick,
I just attempted to generate a bitstream and it failed with the following
errors.
Most messages are the same as before, but take not of the errors present under
"Opt Design"
Vivado Commands
General Messages
[Synth 8-4442] BlackBox module inst_axi_interconnect has unconnected pin
s_ax
Yeah, ok. It's that multiple driver that's the problem. Can you post the
rfnoc_ce_auto_inst.v you're using?
Nick
On Tue, Jan 2, 2018, 10:58 AM Adam Kurisko wrote:
> Nick,
>
>
> I just attempted to generate a bitstream and it failed with the following
> errors.
>
>
> Most messages are the same a
Okay, below I posted my rfnoc_ce_auto_inst.v, as well as, my source code for
noc_block_delay_fifo.v.
- rfnoc_ce_auto_inst.v --
/
// Auto-generated by gen_rfnoc_inst.py! Any changes
// in
Nick,
Haven't heard back from you yet and was just wondering if you were able to give
it a look.
I have a feeling that i may have not instantiated the block correctly in
rfnoc_ce_auto_inst.v, so I am currently attempting to figure out what might be
wrong. Any help or insight into this scenar
Hi Steven,
to answer your question as quickly as possible:
1. Since 3.10.2 and your new version, a revision check was added to the
source code (I just found out; the magic I did was running `git diff
release_003_010_002_000..298a13 db_ubx.cpp` in the right directory). I
preliminarily blame that.
Hi,
so, thinking about this:
I'd hate to be wrong here; so, could you run
usrp_burn_db_eeprom --unit rx
and
usrp_burn_db_eeprom --unit tx
with either version of UHD?
Thank you
Marcus
On Tue, 2018-01-02 at 10:29 -0800, Steven Chen wrote:
> Hi Marcus,
>
> 1. In the previous version (3.10.0
Why have you commented out bus_clk/rst and ce_clk/rst in favor of using
clk/reset? And where are clk/reset/clear being generated? What is being
used as bus_clk/rst in your block's noc_shell?
Nick
On Tue, Jan 2, 2018 at 12:54 PM Adam Kurisko wrote:
> Nick,
>
>
> Haven't heard back from you yet a
Hi Claude,
happy new year to you, too!
So, indeed, this is a bit of a hard problem.
So, which other commands are we referring to? The digital tuning
happens within the DDC RFNoC block; there should be synchronicity.
Generally, the fact that these FIFOs are strictly ordered, of very
finite depth
Hi Marcus,
Running both of those commands returns this:
linux; GNU C++ version 5.4.0 20160609; Boost_105800;
UHD_003.010.002.000-3-g122bfae1
-- X300 initialization sequence...
-- Determining maximum frame size... 8000 bytes.
-- Setup basic communication...
-- Loading values from EEPROM...
--
I actually found that too and reverted it back to the the original bus_clk/rst
and ce_bus/clk such as below:
noc_block_delay_fifo inst_delay_fifo (
.bus_clk(bus_clk), .bus_rst(bus_rst),
.ce_clk(ce_clk), .ce_rst(ce_rst),
.i_tdata(ce_o_tdata[0]), .i_tlast(ce_o_tlast[0]), .i_tvalid(ce_o_tvali
ce_clk is there for you to use as your compute engine clock. If you don't
have a very good reason to generate and use another clock, you should use
that one.
Nick
On Tue, Jan 2, 2018 at 2:57 PM Adam Kurisko wrote:
> I actually found that too and reverted it back to the the original
> bus_clk/rs
Okay, I am now using ce_clk in place of clk for my user code, however now my
implementation is failing with the following error:
Implementation
Opt Design
[DRC 23-20] Rule violation (MDRV-1) Multiple Driver Nets - Net
e310_core0/inst_delay_fifo/noc_shell/out_fifo/fifo_short_2clk/U0/inst_fifo_ge
You're assigning to o_tready and o_tdata instead of s_axis_data_tready and
s_axis_data_tdata.
Incidentally, you're also not setting the "len" input to anything in the
top-level instantiation.
Nick
On Tue, Jan 2, 2018 at 3:22 PM Adam Kurisko wrote:
> Okay, I am now using ce_clk in place of clk
U, marking that as a bug. It's a bit late here, can't test myself,
but can you add "--slot A" to the command line arguments?
Best regards,
Marcus
On Tue, 2018-01-02 at 14:45 -0800, Steven Chen wrote:
> Hi Marcus,
>
> Running both of those commands returns this:
>
> linux; GNU C++ version 5.
On a side note, this is a good time to mention that learning to simulate
RFNoC blocks with the excellent and comprehensive testbench framework
Jonathon put together is the single most effective way to write better
RFNoC blocks, faster. This kind of error would be caught almost instantly
in simulati
Here is the output, interestingly no revision number.
linux; GNU C++ version 5.4.0 20160609; Boost_105800;
UHD_003.010.002.000-3-g122bfae1
-- X300 initialization sequence...
-- Determining maximum frame size... 8000 bytes.
-- Setup basic communication...
-- Loading values from EEPROM...
-- Set
How do I use Jonathon's tb framework? Could you please provide the link to the
manual/instructions if possible?
Also, thank you so much for helping me with this. I am still relatively new to
RFNoC.
Thank you,
Adam
From: Nick Foster
Sent: Tuesday, January 2,
The best way to get started is to look at the existing RFNoC block
testbenches. There are enough that cover enough different configurations
that you should be able to piece a testbench together fairly quickly.
They're in the _tb subfolders of the RFNoC block library.
Nick
On Tue, Jan 2, 2018 at 3
Hi,
I am trying to utilize the digital loopback to check transmitted signal before
DAC in my E312. May I know what is the C++ command to enable the digital
loopback? How to set the SR_LOOPBACK register? In the radio.v, it says,
// Set this register to loop TX data directly to RX data.
s
Now my task will get rid of leakage of oscillator frequency into my
spectrum. Specialists from Yerevan advised me to move the frequency of the
oscilator out of the spectrum as shown in the picture. But with such a
shift, the spectrum changes very much.
__
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