Re: [USRP-users] [X300] UBX-40 v1 compatibility issues.

Steven Chen via USRP-users Tue, 02 Jan 2018 15:38:00 -0800

Here is the output, interestingly no revision number.

linux; GNU C++ version 5.4.0 20160609; Boost_105800;UHD_003.010.002.000-3-g122bfae1


-- X300 initialization sequence...
-- Determining maximum frame size... 8000 bytes.
-- Setup basic communication...
-- Loading values from EEPROM...
-- Setup RF frontend clocking...
-- Radio 1x clock:200
-- [DMA FIFO] Running BIST for FIFO 0... pass (Throughput: 1308.6MB/s)
-- [DMA FIFO] Running BIST for FIFO 1... pass (Throughput: 1304.5MB/s)
-- [RFNoC Radio] Performing register loopback test... pass
-- [RFNoC Radio] Performing register loopback test... pass
-- [RFNoC Radio] Performing register loopback test... pass
-- [RFNoC Radio] Performing register loopback test... pass
-- Performing timer loopback test... pass
-- Performing timer loopback test... pass
Reading RX EEPROM on A dboard...
  Current ID: UBX-40 v1 (0x0078)
  Current serial: "30B1D92"
  Current revision: ""
  Done

-Steve

On 1/2/18 3:34 PM, Marcus Müller wrote:

Uhhhh, marking that as a bug. It's a bit late here, can't test myself,
but can you add "--slot A" to the command line arguments?

Best regards,
Marcus

On Tue, 2018-01-02 at 14:45 -0800, Steven Chen wrote:

Hi Marcus,

Running both of those commands returns this:

linux; GNU C++ version 5.4.0 20160609; Boost_105800;
UHD_003.010.002.000-3-g122bfae1

-- X300 initialization sequence...
-- Determining maximum frame size... 8000 bytes.
-- Setup basic communication...
-- Loading values from EEPROM...
-- Setup RF frontend clocking...
-- Radio 1x clock:200
-- [DMA FIFO] Running BIST for FIFO 0... pass (Throughput:
1300.5MB/s)
-- [DMA FIFO] Running BIST for FIFO 1... pass (Throughput:
1305.0MB/s)
-- [RFNoC Radio] Performing register loopback test... pass
-- [RFNoC Radio] Performing register loopback test... pass
-- [RFNoC Radio] Performing register loopback test... pass
-- [RFNoC Radio] Performing register loopback test... pass
-- Performing timer loopback test... pass
-- Performing timer loopback test... pass
Error: AssertionError: assertion failed:
     is not a valid dboard slot name.
    possible values are: [A, B].

Substituting A, or B into the unit name also returns the same error.

-Steve


On 1/2/18 2:08 PM, Marcus Müller wrote:

Hi,

so, thinking about this:

I'd hate to be wrong here; so, could you run

usrp_burn_db_eeprom --unit rx

and

usrp_burn_db_eeprom --unit tx

with either version of UHD?

Thank you
Marcus

On Tue, 2018-01-02 at 10:29 -0800, Steven Chen wrote:

Hi Marcus,

1. In the previous version (3.10.002) it does recognize the
daughterboard in slot A, I just don't have a daughterboard
populated
in
slot B. I am able use it in a regular fashion (TX/RX).

2. I believe it likely to be what you said about the issues with
the
EEPROM. Is there any reference or documentation for how to go
about
this?

3. This UBX has have been used in a different USRP (X300) before
but
I
believe the X300s are of the same revision, as they were acquired
at
the
same time.

Thanks,

Steven


On 12/31/17 7:17 AM, Marcus Müller wrote:

Hi Steven,

I don't see how the issue is resolved with the previous UHD
version
–
the daughterboard still has ID 0xFFFF and isn't recognized.

So, this is most likely a connection problem. Properly (but
carefully)
reseat the daughterboard, and make sure it's properly screwed
into
place.

If that doesn't help, you might have issues with the
daughterboard
EEPROM, but that would be unusual (albeit fixable).

Now UBX revision 1 is pretty old, so has this been used in
another
USRP
before? This might be critical to know how to approach this.

Best regards,
Marcus


On Wed, 2017-12-13 at 18:50 -0800, Steven Chen via USRP-users
wrote:

I have been having some issues getting a UBX-40v1
daughterboard
recognized with the current master release. When using
"uhd_usrp_probe" I get this error:
[INFO] [UHDlinux; GNU C++ version 5.4.0 20160609;
Boost_105800;
UHD_3.11.0.git-221-g298a13ac]
[INFO] [X300] X300 initialization sequence...
[INFO] [X300] Determining maximum frame size...
[INFO] [X300] Maximum frame size: 8000 bytes.
[INFO] [X300] Setup basic communication...
[INFO] [X300] Loading values from EEPROM...
[INFO] [X300] Setup RF frontend clocking...
[INFO] [X300] Radio 1x clock:200
[INFO] [RFNOC] [DMA FIFO] Running BIST for FIFO 0...
[INFO] [DEBUG] [DMA FIFO] Clock rate for BIST calculation: 0
[INFO] [RFNOC] pass (Throughput: 0.0MB/s)
[INFO] [RFNOC] [DMA FIFO] Running BIST for FIFO 1...
[INFO] [DEBUG] [DMA FIFO] Clock rate for BIST calculation: 0
[INFO] [RFNOC] pass (Throughput: 0.0MB/s)
[INFO] [RFNOC RADIO] Register loopback test passed
[INFO] [RFNOC RADIO] Register loopback test passed
[INFO] [RFNOC RADIO] Register loopback test passed
[INFO] [RFNOC RADIO] Register loopback test passed
[ERROR] [DBMGR] The daughterboard manager encountered a
recoverable
error in init.
Loading the "unknown" daughterboard implementations to
continue.
The daughterboard cannot operate until this error is
resolved.
bad lexical cast: source type value could not be interpreted
as
target
[INFO] [CORES] Performing timer loopback test...
[INFO] [CORES] Timer loopback test passed
[INFO] [CORES] Performing timer loopback test...
[INFO] [CORES] Timer loopback test passed
     _____________________________________________________
    /

        Device: X-Series Device
      _____________________________________________________
     /
    |       Mboard: X300
    |   revision: 11
    |   revision_compat: 7
    |   product: 30817
    |   mac-addr0: 00:80:2f:23:28:76
    |   mac-addr1: 00:80:2f:23:28:77
    |   gateway: 192.168.10.1
    |   ip-addr0: 192.168.20.2
    |   subnet0: 255.255.255.0
    |   ip-addr1: 192.168.50.2
    |   subnet1: 255.255.255.0
    |   ip-addr2: 192.168.30.2
    |   subnet2: 255.255.255.0
    |   ip-addr3: 192.168.40.2
    |   subnet3: 255.255.255.0
    |   serial: 30B4E7A
    |   FW Version: 5.1
    |   FPGA Version: 33.0
    |   FPGA git hash: 000000f
    |   RFNoC capable: Yes
    |
    |   Time sources:  internal, external, gpsdo
    |   Clock sources: internal, external, gpsdo
    |   Sensors: ref_locked
    |     __________________________________________________
___
    |    /
    |   |       RX Dboard: A
    |   |   ID: UBX-40 v1 (0x0078)
    |   |   Serial: 30B1D92

    |   |    /
    |   |   |       RX Frontend: 0
    |   |   |   Name: Unknown (0xffff) - 0
    |   |   |   Antennas:
    |   |   |   Sensors:
    |   |   |   Freq range: 0.000 to 0.000 MHz
    |   |   |   Gain Elements: None
    |   |   |   Bandwidth range: 0.0 to 0.0 step 0.0 Hz
    |   |   |   Connection Type: IQ
    |   |   |   Uses LO offset: No

    |   |    /
    |   |   |       RX Codec: A
    |   |   |   Name: ads62p48
    |   |   |   Gain range digital: 0.0 to 6.0 step 0.5 dB
    |     __________________________________________________
___
    |    /
    |   |       RX Dboard: B

    |   |    /
    |   |   |       RX Frontend: 0
    |   |   |   Name: Unknown (0xffff) - 0
    |   |   |   Antennas:
    |   |   |   Sensors:
    |   |   |   Freq range: 0.000 to 0.000 MHz
    |   |   |   Gain Elements: None
    |   |   |   Bandwidth range: 0.0 to 0.0 step 0.0 Hz
    |   |   |   Connection Type: IQ
    |   |   |   Uses LO offset: No

    |   |    /
    |   |   |       RX Codec: B
    |   |   |   Name: ads62p48
    |   |   |   Gain range digital: 0.0 to 6.0 step 0.5 dB
    |     __________________________________________________
___
    |    /
    |   |       TX Dboard: A
    |   |   ID: UBX-40 v1 (0x0077)
    |   |   Serial: 30B1D92

    |   |    /
    |   |   |       TX Frontend: 0
    |   |   |   Name: Unknown (0xffff) - 0
    |   |   |   Antennas:
    |   |   |   Sensors:
    |   |   |   Freq range: 0.000 to 0.000 MHz
    |   |   |   Gain Elements: None
    |   |   |   Bandwidth range: 0.0 to 0.0 step 0.0 Hz
    |   |   |   Connection Type: IQ
    |   |   |   Uses LO offset: No

    |   |    /
    |   |   |       TX Codec: A
    |   |   |   Name: ad9146
    |   |   |   Gain Elements: None
    |     __________________________________________________
___
    |    /
    |   |       TX Dboard: B

    |   |    /
    |   |   |       TX Frontend: 0
    |   |   |   Name: Unknown (0xffff) - 0
    |   |   |   Antennas:
    |   |   |   Sensors:
    |   |   |   Freq range: 0.000 to 0.000 MHz
    |   |   |   Gain Elements: None
    |   |   |   Bandwidth range: 0.0 to 0.0 step 0.0 Hz
    |   |   |   Connection Type: IQ
    |   |   |   Uses LO offset: No

    |   |    /
    |   |   |       TX Codec: B
    |   |   |   Name: ad9146
    |   |   |   Gain Elements: None
    |     __________________________________________________
___
    |    /
    |   |       RFNoC blocks on this device:
    |   |
    |   |   * DmaFIFO_0
    |   |   * Radio_0
    |   |   * Radio_1
    |   |   * DDC_0
    |   |   * DDC_1
    |   |   * DUC_0
    |   |   * DUC_1

Rolling back to an earlier version seems to resolve this
issue.

linux; GNU C++ version 5.4.0 20160609; Boost_105800;
UHD_003.010.002.HEAD-0-gbd6e21dc
-- X300 initialization sequence...
-- Determining maximum frame size... 8000 bytes.
-- Setup basic communication...
-- Loading values from EEPROM...
-- Setup RF frontend clocking...
-- Radio 1x clock:200
-- [DMA FIFO] Running BIST for FIFO 0... pass (Throughput:
1304.6MB/s)
-- [DMA FIFO] Running BIST for FIFO 1... pass (Throughput:
1304.0MB/s)
-- [RFNoC Radio] Performing register loopback test... pass
-- [RFNoC Radio] Performing register loopback test... pass
-- [RFNoC Radio] Performing register loopback test... pass
-- [RFNoC Radio] Performing register loopback test... pass
-- Performing timer loopback test... pass
-- Performing timer loopback test... pass
     _____________________________________________________
    /

        Device: X-Series Device
      _____________________________________________________
     /
    |       Mboard: X300
    |   revision: 11
    |   revision_compat: 7
    |   product: 30817
    |   mac-addr0: 00:80:2f:23:28:76
    |   mac-addr1: 00:80:2f:23:28:77
    |   gateway: 192.168.10.1
    |   ip-addr0: 192.168.20.2
    |   subnet0: 255.255.255.0
    |   ip-addr1: 192.168.50.2
    |   subnet1: 255.255.255.0
    |   ip-addr2: 192.168.30.2
    |   subnet2: 255.255.255.0
    |   ip-addr3: 192.168.40.2
    |   subnet3: 255.255.255.0
    |   serial: 30B4E7A
    |   FW Version: 5.1
    |   FPGA Version: 33.0
    |   RFNoC capable: Yes
    |
    |   Time sources:  internal, external, gpsdo
    |   Clock sources: internal, external, gpsdo
    |   Sensors: ref_locked
    |     __________________________________________________
___
    |    /
    |   |       RX Dboard: A
    |   |   ID: UBX-40 v1 (0x0078)
    |   |   Serial: 30B1D92

    |   |    /
    |   |   |       RX Frontend: 0
    |   |   |   Name: UBX RX
    |   |   |   Antennas: TX/RX, RX2, CAL
    |   |   |   Sensors: lo_locked
    |   |   |   Freq range: 10.000 to 6000.000 MHz
    |   |   |   Gain range PGA0: 0.0 to 31.5 step 0.5 dB
    |   |   |   Bandwidth range: 40000000.0 to 40000000.0
step
0.0 Hz
    |   |   |   Connection Type: IQ
    |   |   |   Uses LO offset: No

    |   |    /
    |   |   |       RX Codec: A
    |   |   |   Name: ads62p48
    |   |   |   Gain range digital: 0.0 to 6.0 step 0.5 dB
    |     __________________________________________________
___
    |    /
    |   |       RX Dboard: B

    |   |    /
    |   |   |       RX Frontend: 0
    |   |   |   Name: Unknown (0xffff) - 0
    |   |   |   Antennas:
    |   |   |   Sensors:
    |   |   |   Freq range: 0.000 to 0.000 MHz
    |   |   |   Gain Elements: None
    |   |   |   Bandwidth range: 0.0 to 0.0 step 0.0 Hz
    |   |   |   Connection Type: IQ
    |   |   |   Uses LO offset: No

    |   |    /
    |   |   |       RX Codec: B
    |   |   |   Name: ads62p48
    |   |   |   Gain range digital: 0.0 to 6.0 step 0.5 dB
    |     __________________________________________________
___
    |    /
    |   |       TX Dboard: A
    |   |   ID: UBX-40 v1 (0x0077)
    |   |   Serial: 30B1D92

    |   |    /
    |   |   |       TX Frontend: 0
    |   |   |   Name: UBX TX
    |   |   |   Antennas: TX/RX, CAL
    |   |   |   Sensors: lo_locked
    |   |   |   Freq range: 10.000 to 6000.000 MHz
    |   |   |   Gain range PGA0: 0.0 to 31.5 step 0.5 dB
    |   |   |   Bandwidth range: 40000000.0 to 40000000.0
step
0.0 Hz
    |   |   |   Connection Type: QI
    |   |   |   Uses LO offset: No

    |   |    /
    |   |   |       TX Codec: A
    |   |   |   Name: ad9146
    |   |   |   Gain Elements: None
    |     __________________________________________________
___
    |    /
    |   |       TX Dboard: B

    |   |    /
    |   |   |       TX Frontend: 0
    |   |   |   Name: Unknown (0xffff) - 0
    |   |   |   Antennas:
    |   |   |   Sensors:
    |   |   |   Freq range: 0.000 to 0.000 MHz
    |   |   |   Gain Elements: None
    |   |   |   Bandwidth range: 0.0 to 0.0 step 0.0 Hz
    |   |   |   Connection Type: IQ
    |   |   |   Uses LO offset: No

    |   |    /
    |   |   |       TX Codec: B
    |   |   |   Name: ad9146
    |   |   |   Gain Elements: None
    |     __________________________________________________
___
    |    /
    |   |       RFNoC blocks on this device:
    |   |
    |   |   * DmaFIFO_0
    |   |   * Radio_0
    |   |   * Radio_1
    |   |   * DDC_0
    |   |   * DDC_1
    |   |   * DUC_0
    |   |   * DUC_1

I tested this on another X300 with TwinRXs installed and they
seem to
initialize fine with both versions. I am wondering if it is
specific
to the UBX board.

Thanks,
Steve
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Re: [USRP-users] [X300] UBX-40 v1 compatibility issues.

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