Hi,
I'm currently trying to find out a way to simulate the entire b210 architecture.
I've find a "run_sim" command located in the directory :
prefix/rfnoc/src/uhd-fpga/usrp3/top/b200/sim/b2x0/sim_b2x0_1
This command tried to run ISim but all the links looks broken. I've tried to
figure out th
Hi Marcus,
How do i produce a sum of multiple tones using the uhd libraries?
tx_waveforms.cpp lets me set a center frequency with uhd::tune_request_t
tune_request(LO_freq), but what I want is to see an output A1*sin(f1*t +
phi1) + A2 * sin(f2*t + phi2) + ...
Along similar lines, how do I change t
Hi Dario,
Interesting. I would expect 2 UBX-160 with 2 radio blocks into the 2 input
ports to work. My best guess is that there is some issue with either the
detected upstream nodes or the propagation of the stream command. It would
be interesting to debug the source_block_ctrl_base::issue_stre
A quick note from the other Marcus.
The UHD library is NOT a DSP library. If you need to "do things to my
signal", you'll need to do that outside of UHD itself, which is really
just a driver API for the hardware.
This is the domain of software systems like Gnu Radio, or if you're
doing this in
So as far as using Verilog goes, how would I remove the offset (as
described in the original post)?
I don't think I can use gnuradio because the sample rate maxes out at
around 5 Msps (if I try to push past this, I get "The total sum of rates
exceeds the maximum capacity of the connection), so for
Never use a throttle in a flow that includes actual hardware.
You're probably connecting via USB-2.0, which wont' support two channels
at 5Msps.
The tuned center frequency has nothing to do with the sample rate. The
sample rate determines the bandwidth centered around your center
frequency th
Hi,
I was wondering if anyone has the materials for the famous talk by Matt
Ettus in 2011 GRCon.
*"Why Doesn't My Signal Look Like the Textbook?"*
I remember it was hosted on Tom's webpage. The link is still there, however
the files are missing.
http://www.trondeau.com/grc2011-abstracts/
Go to
Matt gave this talk again at GR Con 2015 in Boulder. Slides here:
https://drive.google.com/file/d/0B6ccrJyAZaq3UHpEQld1YmZjbWs/view
On Mon, Oct 16, 2017 at 1:56 PM, Sumit Kumar via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Hi,
>
> I was wondering if anyone has the materials for the famou
Thanks Robin, I found the slides. However the talk which he gave in GRCon
2011 was approx 3:30 hr long.
Anyways do you also have the grc files used in the slides !
Thanks much
Sumit
On Mon, Oct 16, 2017 at 11:21 PM, Robin Coxe wrote:
> Matt gave this talk again at GR Con 2015 in Boulder. Slid
Hi Felipe,
1) As with any custom RFNoC block, yes it would connect to the crossbar.
2) Yes, your understanding is correct.
3) You would have to define what "high latency" is. The block would
certainly add latency to the path. I would expect it to be on the order of
1 packet due to packet ga
How would I then include negative numbers on the Verilog side to kill the
offset? I'm a bit more comfortable with fpga design than with SDR, so for
testing purposes I'd prefer to do it that way.
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I am pretty sure those blocks all made it into GR core. Check the examples
sections.
On Mon, Oct 16, 2017 at 5:25 PM Sumit Kumar via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Thanks Robin, I found the slides. However the talk which he gave in GRCon
> 2011 was approx 3:30 hr long.
>
> Anyw
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