Dear Martin,
So, CIC's status is a binary one. For example if the ratio is 3, 3%4 = 3
and because there is a remainder, the CIC is enabled. If the ratio is 20,
both half-bands will be enabled and CIC is disabled as 20%4 = 0. Did I
understand correctly?
Regards,
Altug
On Tue, Jul 18, 2017 at 5:59
Hello Altug,
The CIC can be programed to decimate by a range of integer amounts. If the
ratio is 20 (50 MHz sampling rate, 2.5 MHz output rate) then both half
bands will be used (divide by 2*2) and the CIC will decimate by 5. Odd CIC
rates have poor filter roll off compared to even rates.
Derek
Hello all,
The release candidate of UHD version 3.10.2.0 has been tagged and is
available for testing. There have been no API breaking changes necessary
since the last release but a small ABI change means we are incrementing the
ABI number. Updated FPGA and firmware images have been uploaded.
The
Hi,
Is there any example codes or reference on how to configure the B210 to TDD
mode? Thanks.
Jay
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Martin,
I CentOS 6.5 comes with python 2.6, however, I believe I need python 2.7. I
currently install python 2.7 and attempt to set up a virtual environment.
Mark
On 7/19/17, 12:02 PM, "USRP-users on behalf of
usrp-users-requ...@lists.ettus.com" wrote:
Centos 6.5 with X310??
__
Could this have something to do with tlast? I don't feel like it is the
XML files, so I am limited to looking at the verilog, but it is pretty
similar to my other blocks, so I am not sure what the problem could be.
It is odd to me that the probing is enough to cause issues, I am not
sure what
Hi all,
as far as I'm aware, the two daughter boards on the x310 device each allow
for full duplex communication simultaneously. In other words, I should be
able to connect a string of (or a ring network too) for e.g. three x310
devices together. Assuming the answer to that is yes, are there any
s
;s status is a binary one. For example if the ratio is 3, 3%4 = 3
and because there is a remainder, the CIC is enabled. If the ratio is 20,
both half-bands will be enabled and CIC is disabled as 20%4 = 0. Did I
understand correctly?
Regards,
Altug
On Tue, Jul 18, 2017 at 5:59 PM, Martin Braun via USRP-users <
u
se will have the same requirements.
I think that CentOS 6.5 doesnt' meet all the requirements (maybe Boost
is too old or something), but I'm pretty sure that people have built UHD
on older CentOSes. Which Python version do you have? Maybe you can use
PyBOMBS which'll automate building everything from source.
Cheers,
Marti
k_rate that is divisible by 4 has 2
half-bands, any other even ratio has 1 half-band, and the remainder is
done in the CIC.
Cheers,
Martin
On 07/18/2017 07:55 AM, altu? kaya via USRP-users wrote:
Hello everyone,
In B210 there are 2 half-band filters and 4 CIC filters. As far as I
know we can selec
In radio_legacy.v there is example code for adding user registers. Namely:
generate
if (USER_SETTINGS == 1) begin
wire set_stb_user;
wire [7:0] set_addr_user;
wire [31:0]set_data_user;
wire [7:0] rb_addr_user;
user_settings #(.BASE(SR_USER_S
Is your source block always trying to outputting packets? If so, your block
could be trying to send packets while noc_shell is initializing. The easy
fix is to add an enable register to hold off your block until after
initialization.
On Wed, Jul 19, 2017 at 9:44 AM, Jason Matusiak via USRP-users <
Ah, that does sound like the issue. How do i know it is done initializing? You
dont do something similar in the siggen block thoigh, right?
Sent from my Verizon, Samsung Galaxy smartphone
Original message From: Jonathon Pendlum
Date: 7/19/17 5:34 PM (GMT-05:00) To: Jason
Matu
Hello Nathan:
We have some further information posted here:
https://kb.ettus.com/TwinRX#RF_Specifications
We are working on a much more comprehensive set of data, but we do not yet
have a date for when that will be available.
Is there something specific that you're looking for?
--Neel Pandeya
Hello Amirhosein:
Could you please describe this issue in more detail? What gain setting are
you using? What is your input power?
Please note that you should not input more than -15 dBm into the SBX at any
time.
--Neel Pandeya
On 29 April 2017 at 00:53, Amirhosein naseri via USRP-users <
us
Hello Deepa Kumar:
There is no watchdog timer on the E310/E312.
What exactly are you trying to do? There might be another way to implement
what you want.
--Neel Pandeya
On 17 July 2017 at 07:00, deepa kumar via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Hi ,
>
> Can I have more deta
Hello Sean:
You are correct that the control voltage is changed/updated every 1 second.
Unfortunately, there is no simple register setting in the FPGA for the gain
value applied to the detected error. The only way to change the gain value
is to build an FPGA image with custom changes. For a PPS in
Hello liu Jong:
The 153933B-11L number is an assembled board, a Completed Circuit Assembly
(CCA), a populated board, and the 153934B-01 number is a schematic.
Basically, there is no difference between the two part numbers in terms of
any difference in the schematic. The file posted on-line is up-
Hi all,
We used B210 with TCXO,and run about 2 hours , a 3.2K frequency shift
occurred when the temperature did not change significantly.Is it a normal?
How can we improve this situation?
thank you.
best regards
John
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On 07/19/2017 11:46 PM, john liu via USRP-users wrote:
Hi all,
We used B210 with TCXO,and run about 2 hours , a 3.2K frequency shift
occurred when the temperature did not change significantly.Is it a normal?
How can we improve this situation?
thank you.
best regards
John
What was your tuned
Hello Maurizio:
I have not reviewed your code in detail, but a circular buffer using two
separate threads, one for writing into the buffer, and one for reading from
the buffer and writing to the SD card, seems like a reasonable approach.
You will be limited by how fast samples can be DMA'd from th
Hello USRP Users
I was able to develop an *FPGA based loop back which directs the raw ADC
data to the DAC* . The TX transmits whatever it sees on the receive signal
path.
The loop back works as expected for sampling rates upto 30 MSps but it
fails to loopback received signals at a *higher sampling
>
>
>
> What was your tuned frequency in this case?
Hi,Marcus,
It is 433.05Mhz
On Thu, Jul 20, 2017 at 11:46 AM, john liu wrote:
> Hi all,
> We used B210 with TCXO,and run about 2 hours , a 3.2K frequency shift
> occurred when the temperature did not change significantly.Is it a normal?
> How
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