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, Brendon - 0551 - MITLL ;
USRP-users@lists.ettus.com
Subject: Re: [USRP-users] RFNoc Blocks with Xilinx IP
Hi Brendon,
I went ahead and updated the OOT example repo to be compatible with Vivado
2017.4 and the uhd-fpga "master" branch:
https://github.com/ejk43/rfnoc-ootexamp
Hi Brendon,
I went ahead and updated the OOT example repo to be compatible with Vivado
2017.4 and the uhd-fpga "master" branch:
https://github.com/ejk43/rfnoc-ootexample
The simulation testbenches now run using uhd-fpga master. Let me know if
this works for you. Thanks!
EJ
On Fri, Jul 20, 2018 a
Hi Brendon,
I have an example repo that shows how to use out-of-tree makefiles with
xilinx IP (.xci definitions): github.com/ejk43/rfnoc-ootexample
Please feel free to copy this format- a few other rfnoc developers on the
mailing list indicated it has worked for them too.
Note that the rfnoc bl
Hello Brendon:
Could you describe in more detail what you're trying to do, or how you want
to add your Xilinx IP?
Are you still using "rfnocmodtool" to add your custom RFNoC blocks?
The flow described in that document, and in the Application Note below, is
the primary/intended way to add IP to a
