EJ,
The help is much appreciated!
- Brendon
============================================================================
Brendon Chetwynd Technical Staff
MIT Lincoln Laboratory
Cyber Systems and Operations (Group 51)
244 Wood Street Lexington, MA 02420-9185
781-981-8212 (office)
brendon.chetw...@ll.mit.edu 781-879-4635 (cell)
781-387-3030 (pager)
781-981-7548 (fax)
============================================================================
From: EJ Kreinar <ejkrei...@gmail.com>
Sent: Saturday, July 21, 2018 6:59 PM
To: Neel Pandeya <neel.pand...@ettus.com>
Cc: Chetwynd, Brendon - 0551 - MITLL <brendon.chetw...@ll.mit.edu>;
USRP-users@lists.ettus.com
Subject: Re: [USRP-users] RFNoc Blocks with Xilinx IP
Hi Brendon,
I went ahead and updated the OOT example repo to be compatible with Vivado
2017.4 and the uhd-fpga "master" branch:
https://github.com/ejk43/rfnoc-ootexample
The simulation testbenches now run using uhd-fpga master. Let me know if this
works for you. Thanks!
EJ
On Fri, Jul 20, 2018 at 1:01 PM EJ Kreinar <ejkrei...@gmail.com
<mailto:ejkrei...@gmail.com> > wrote:
Hi Brendon,
I have an example repo that shows how to use out-of-tree makefiles with xilinx
IP (.xci definitions): github.com/ejk43/rfnoc-ootexample
<http://github.com/ejk43/rfnoc-ootexample>
Please feel free to copy this format- a few other rfnoc developers on the
mailing list indicated it has worked for them too.
Note that the rfnoc blocks are currently targeting the uhd-fpga source code as
of Vivado 2015.4, and the testbenches will NOT currently run against most
recent uhd-fpga and Vivado 2017.4. I would really appreciate a PR to update the
IP to use vivado 2017.4 and noc blocks with the new inputs to the noc_shell :)
I'll update it "eventually" but no idea when exactly.
Hope this helps! Looking forward to seeing your OOT fpga blocks :)
EJ
On Fri, Jul 20, 2018, 12:19 PM Neel Pandeya via USRP-users
<usrp-users@lists.ettus.com <mailto:usrp-users@lists.ettus.com> > wrote:
Hello Brendon:
Could you describe in more detail what you're trying to do, or how you want to
add your Xilinx IP?
Are you still using "rfnocmodtool" to add your custom RFNoC blocks?
The flow described in that document, and in the Application Note below, is the
primary/intended way to add IP to an RFNoC installation.
https://kb.ettus.com/Getting_Started_with_RFNoC_Development
Please note that you should use the head of the UHD master branch, not the
"rfnoc-devel" branch, when using RFNoC.
--​Neel Pandeya
On 20 July 2018 at 07:01, Chetwynd, Brendon - 0551 - MITLL via USRP-users
<usrp-users@lists.ettus.com <mailto:usrp-users@lists.ettus.com> > wrote:
I have been following the following blog post:
http://www.synchronouslabs.com/blog/creating-a-custom-rfnoc-block-with-using-xillinx-ip
Near the end, it instructs the user to add the Xilinx IP files (.xci for
example) to the UHD project directory.
However, as this is a clone of the Ettus Research repo
(https://github.com/EttusResearch/fpga.git), I am wondering if there is another
way to do it that is compliant with the RFNOC build process.
Specifically, I would like to drop my customized Xilinx IP within my own rfnoc
repository.
Any advice?
Thanks,
Brendon
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