No. I did not change anything in the default image. It is true that the
default image is routed such that the Replay block uses dynamic routing
through a streaming endpoint to stream data to the DUC. Each Replay block
port connects to an individual endpoint such that there is not a bandwidth
limi
Hi Rob,
Thank you once again for answering my question!
I have one more question?
Did you change anything in the default FPGA image, in order to be able to
sustain a maximum 125 MS/s for 4 channels on N310, or 200 MS/s for 2
channels on X310?
By looking into x310_rfnoc_image_core.yml and the sa
Hi Emil,
With UHD 4.0, this works. And, the latest FPGA images from Ettus include
the Replay block on the X310 (in the past, this was just for the N310) so
you don't even have to build your own image. And, the latest FPGA images
provide access to the full 1GB ram such that you could store arb wave
