Hi all,
Thanks for all of your help. Once I annotated the signals to debug, Vivado
started failing on creating a bitstream. It turns out I had labeled the
wrong direction for the master tready signal which in default synthesis was
driven to 0.
Thanks,
Andrew
On Fri, Dec 21, 2018 at 11:33 AM Andr
Hi all,
I tried building a control block like the one on github, but still no luck.
I have a jtag kit on the way, so I'll keep you posted.
Thanks!
Andrew
On Wed, Dec 19, 2018 at 7:15 PM Jon Pendlum wrote:
> Hi Andrew,
>
> You'll need to have a Xilinx USB programmer (or Digilent JTAG-HS3 probab
Hi Andrew,
You'll need to have a Xilinx USB programmer (or Digilent JTAG-HS3 probably
works too), purchase this kit https://www.ettus.com/product/details/E-JTAG-4,
and follow these instructions:
https://www.ettus.com/content/files/E-Series_JTAG-AVR_Cable_Getting_Started_Guide_.pdf.
For setting up
Hi John,
Is there any documentation on using the ILA on an e310 that's running
gnuradio directly?
Thanks,
Andrew
On Tue, Dec 18, 2018 at 8:36 PM Jon Pendlum wrote:
> Hi Andrew,
>
> Have you tried using Chipscope to see where the issue is at in your code?
> You want to look at the tvalid and tr
Hi Andrew,
Have you tried using Chipscope to see where the issue is at in your code?
You want to look at the tvalid and tready AXI stream control signals to
pinpoint where your data flow stalls (i.e. tvalid = 1 and tready = 0). Once
you know where the stall is located, I can provide more advice.
Some more thoughts...
Are you programming the axi_rate_change SR_N, SR_M, and SR_CONFIG registers
when you run on hardware? You might be able to do this with the XML
definition, but you may also need a block controller like the
ddc_block_ctrl_impl in uhd. Don't forgot the config register-- this se
Thanks for the reply. I do set simple_mode and I propagate tuser into and
out of axi_rate_change the same way noc_block_ddc does. I also have my
block running properly in Vivado simulation. Is there anything else I
should check? I also included axi_tag_time. Could that be causing an issue?
Thanks!
Hi Andrew,
Quick thoughts:
- Are you setting SIMPLE_MODE(0) in the axi_wrapper?
- Are you propagating tuser into and out of the axi_rate_change block?
The axi_rate_change block updates tuser, which the axi_wrapper uses to
create output packets when SIMPLE_MODE is disabled.
Also, have you run in
