Re: [USRP-users] x310 simulating RFNoC block with Xilinx IP

2018-09-04 Thread Dang tien Vo-Huu via USRP-users
Hi Martin, I was able to run the simulation when I modified setupenv_base.sh to replace the default path to Vivado with my custom path ( I think it should be the same as --vivado-path= ) and also "source uhd-fpga/usrp3/top/x300/setupenv.sh". Thank you. Best, Tien On Tue, Sep 4, 2018 at 5:33 PM Ma

Re: [USRP-users] x310 simulating RFNoC block with Xilinx IP

2018-09-04 Thread Martin Braun via USRP-users
On Fri, Feb 09, 2018 at 12:44:26PM -0500, Dang tien Vo-Huu wrote: >Hi Martin, >I am on branch rfnoc-devel at version >b0890fa97ef3dc7d90ed8047d678ca280c72ad61, and I am using Vivado 2015.4 >- >tienvh@gl502vm:~/workspace/rfnoc/s

Re: [USRP-users] x310 simulating RFNoC block with Xilinx IP

2018-02-09 Thread Dang tien Vo-Huu via USRP-users
Hi Martin, I am on branch rfnoc-devel at version b0890fa97ef3dc7d90ed8047d678ca280c72ad61, and I am using Vivado 2015.4 - tienvh@gl502vm:~/workspace/rfnoc/src/uhd-fpga$ git branch * rfnoc-devel tienvh@gl502vm:~/workspace/rfnoc/src/uhd-fpga$ git

Re: [USRP-users] x310 simulating RFNoC block with Xilinx IP

2018-02-09 Thread Martin Braun via USRP-users
On 01/30/2018 08:08 AM, Dang tien Vo-Huu via USRP-users wrote: > Hi Jonathon, > Thank you for the hint. Actually your suggestion was the first thing I > tried but it didn't work. It threw the error: > > tienvh@gl502vm:~/workspace/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_block_fft_tb$ > make xsim > B

Re: [USRP-users] x310 simulating RFNoC block with Xilinx IP

2018-01-30 Thread Dang tien Vo-Huu via USRP-users
Hi Jonathon, Thank you for the hint. Actually your suggestion was the first thing I tried but it didn't work. It threw the error: tienvh@gl502vm:~/workspace/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_block_fft_tb$ make xsim BUILDER: Checking tools... * GNU bash, version 4.3.48(1)-release (x86_64-pc-li

Re: [USRP-users] x310 simulating RFNoC block with Xilinx IP

2018-01-29 Thread Jon Pendlum via USRP-users
Hi Tien, Run 'make xsim' in the same directory as the testbench. Jonathon On Jan 22, 2018 12:52 PM, "Dang tien Vo-Huu via USRP-users" < usrp-users@lists.ettus.com> wrote: Hi EJ, It works! Now I am able to simulate the custom block with IP in both cases. Just another small question, can we simul

Re: [USRP-users] x310 simulating RFNoC block with Xilinx IP

2018-01-22 Thread Dang tien Vo-Huu via USRP-users
Hi EJ, It works! Now I am able to simulate the custom block with IP in both cases. Just another small question, can we simulate the built-in RFNoC block? I see the simulate file (for example noc_block_fft_tb.sv) but not sure how to run it.. Thank you very much for the help. Best, Tien On Mon, Ja

Re: [USRP-users] x310 simulating RFNoC block with Xilinx IP

2018-01-22 Thread EJ Kreinar via USRP-users
Hi Tien, If the Xilinx IP is included in the uhd-fpga/usrp3/lib repo, you can follow the example provided in the Makefile for the noc_block_fft_tb: https:// github.com/EttusResearch/fpga/blob/rfnoc-devel/usrp3/lib/ rfnoc/noc_block_fft_tb/Makefile Note the three steps: 1. set LIB_IP_DIR 2. Include

[USRP-users] x310 simulating RFNoC block with Xilinx IP

2018-01-20 Thread Dang tien Vo-Huu via USRP-users
Hi all, I have this error when trying to simulate a custom RFNoC block in an OOT module: $ make noc_block_hbFilter_tb . . Starting static elaboration ERROR: [VRFC 10-2063] Module not found while processing module instance [/home/tienvh/workspace/rfnoc/src/rfnoc-filters/rfnoc/fpga-src/noc