Hello Peter,
thank you for noticing this. We will take care of this shortly.
- Nicolas
On Tue, May 8, 2018 at 10:57 AM, Peter Horvath via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Hello,
>
> the clocking scheme has been recently changed, as of
> https://github.com/EttusResearch/fpga/com
Hello,
the clocking scheme has been recently changed, as of
https://github.com/EttusResearch/fpga/commit/89957c3f30d3e17ddd43622277cbec299b207805
But it seems that the rfnocmodtool Verilog template did not receive the
required changes, i.e., it leaves bus_clk and reset unconnected on the
axi_wrap
